Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Reexamination Certificate
2000-04-19
2002-12-10
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular signal path connections
C257S207000, C257S691000, C257S692000
Reexamination Certificate
active
06492667
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a radio frequency (RF) semiconductor apparatus, and more particularly, to an electrical connection structure for achieving excellent radio frequency characteristics in a radio frequency semiconductor apparatus which operates in the gigahertz (GHz) band.
2. Description of the Related Art
In recent years, the need for integrated circuits operating in the microwave or millimeter wave band has increased as a result of the widespread use of mobile communications means such as PHS (Personal Handy Phone System) and PDC (Personal Digital Cellular phone).
As a result, the development of Si or GaAs transistors has advanced enough to produce highly-integrated MMICs (Monolithic Microwave Integrated Circuits) incorporating such transistors, e.g., power amplifiers, mixers, and low-noise amplifiers.
In such an integrated circuit operating in a radio frequency band, more than negligible parasitic inductance may exist which significantly affects the characteristics of the integrated circuit.
For example, when a RF semiconductor circuit chip is mounted in a package or on a substrate, bonding wires used for electrical connection purposes tend to have a substantial inductance component. In order to obtain the expected circuit performance of the RF semiconductor circuit chip, it is important to minimize such inductance components.
While it is possible to reduce the inductance component residing in a signal line extended from a RF semiconductor circuit chip through impedance matching with an externally-connected load circuit, the inductance component residing in a ground line cannot be controlled through such impedance matching.
Thus, in the case of mounting a RF semiconductor circuit chip composed of, e.g., gallium arsenide (GaAs), it is essential to connect the ground line to a grounding surface in such a manner that the inductance associated with the ground line within the chip is minimized. Otherwise, the above-mentioned inductance tends to reduce the gain of any amplification circuit within the chip, particularly in a RF band.
Conventional methods for reducing the above-mentioned inductance fall into two major categories. One category is employed in the case, for example, where a GaAs integrated circuit chip is mounted on a package and electrically connected by wire bonding. These methods amount to increasing as much as possible the number of bonding wires which extend from bonding pads within the chip to be each connected to either a lead frame or a slug which is located immediately below the chip. In other words, a plurality of bonding wires each having a certain inductance value are arranged in parallel connection so as to reduce the total inductance of the bonding wires.
FIG. 3
is a schematic diagram illustrating the above-described method of arranging bonding wires in such a parallel connection. This example illustrates wire bonding for an output stage of an amplifier circuit within a multitransistor unit.
In
FIG. 3
,
1
denotes an IC chip;
2
denotes an output stage transistor within the chip;
3
denotes a bonding pad on the chip;
4
denotes a signal line (bonding wire);
5
denotes a ground line (bonding wire);
7
denotes a signal lead frame pin;
8
denotes a grounding point; and
9
denotes a substrate. The grounding point
8
is typically a metal portion (usually referred to as “slug”) exposed on a back face of a package; otherwise a grounding lead frame pin may be used.
In the example shown in
FIG. 3
, four bonding wires are used as the ground lines
5
for grounding emitters of the output stage transistor
2
within the IC chip
1
.
The other category for reducing the inductance of a bonding wire involves reducing the length of the bonding wires. According to the methods in this category, a portion on a chip to be die-bonded is arranged so as to be lower than the other portions of the chip. In this manner, the height of the bonding pads on the chip is matched to that of the patterned circuitry on the surface of the substrate. As a result, the length of the bonding wires is shortened, thereby reducing the inductance values of the bonding wires. Such methods are disclosed in Japanese Laid-open Publication No. 2-107001 and Japanese Laid-open Publication No. 3-262302, for example.
Another method to shorten the length of a lead wire is to make a very small hole into a GaAs integrated circuit chip so that a ground line within the chip can be connected to a ground surface on the back face of the chip through this hole.
However, the aforementioned conventional methods for minimizing inductance components have the following problems.
A plurality of grounding bonding wires may be arranged in parallel in an attempt to reduce the inductance in the ground lines. However, as the number of bonding wires increases, the chip size will become larger due to the space required for the wires if the intervals between the bonding wires remain unchanged. In other words, in order to prevent a decrease in the packing density on the chip, the intervals between the bonding wires should be made narrow. However, narrower intervals between the bonding wires causes electromagnetic coupling between adjacent bonding wires, thereby resulting in an increased mutual inductance between the wires. Therefore, simply introducing an increased number of bonding wires may not necessarily reduce the total inductance as desired.
The above problem is illustrated in
FIG. 4
, which is a graph illustrating the relationship between the number of bonding wires (length: about 1 mm) which are arranged in parallel at an interval of about 140 &mgr;m and the equivalent inductance value thereof as estimated by an electromagnetic field simulation. Illustrated for comparison are the inductance values obtained by dividing the simulated result for one wire by different numbers of wires.
The simulation was conducted under the conditions of an operating frequency of about 2 GHz and a signal line impedance of about 2&OHgr; (assuming an output stage transistor for a power amplifier).
As shown in
FIG. 4
, the equivalent inductance value of the bonding wires does not decrease in exact inverse proportion to the number of wires (as would be expected absent the effects of mutual inductance). Rather, the equivalent inductance value remains higher than the expected value. This is presumably caused by a so-called mutual inductance phenomenon, in which the in-phase magnetic fields occurring around the wires affect adjacent wires so as to prevent currents from passing therethrough.
In the simulation in
FIG. 4
, the interval between the bonding wires was kept constant at about 140 &mgr;m regardless of the number of wires. As previously described, the mutual inductance increases as the interval between the bonding wires decreases. Therefore, it will be understood that the equivalent inductance-reducing effect associated with an increase in the number of wires is attenuated as the interval between the bonding wires decreases, because of increased mutual inductance.
FIG. 5
is a graph illustrating a MAG (Maximum Available Gain: a maximum gain obtained through complete input/output impedance matching) of an amplification circuit incorporating an output stage transistor, where the results of the graph in
FIG. 4
are applied to a ground line
5
extending from the emitter of the output stage transistor. This simulation was conducted in order to determine MAG values at an operating frequency of about 2 GHz.
As shown in
FIGS. 4 and 5
, the equivalent inductance of bonding wires can be reduced as the number of wires is increased, thereby making it possible to obtain a large gain in an amplification circuit incorporating such bonding wires. However, an increased number of wires would result in a larger chip size due to a corresponding increase in the number of bonding pads on the chip, as mentioned before, thereby resulting in higher manufacturing costs.
On the other hand, decreasing the interval between the bonding wires to avoid an increase in the chip size will not
Cao Phat X.
Nixon & Vanderhye PC
Sharp Kabushiki Kaisha
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