Method for reducing translation look aside buffer purges in a mu

Details Method for reducing translation look aside buffer purges in a mu Method for reducing translation look aside buffer purges in a mu

1992-04-29

1995-06-27

Robertson, David L.

Boots, shoes, and leggings

395425, 364DIG1, 3642564, G06F 1210, G06F 1208

Patent

active

054287570

ABSTRACT:
A process for reducing translation look-aside buffer (TLB) purge overhead does so by purging the TLB only when required to avoid invalid entries. The translation look-aside buffer (TLB) contains virtual to real mappings for a particular address space. Operating systems commonly purge the TLB whenever a new task is dispatched to ensure the TLB entries are valid. A system with relatively short tasks will incur significant overhead by this practice. The present invention detects those situations where a purge is required by associating TLB purge with the address space allocation logic. Invalid TLB entries will exist only where an address space is re-used by a different task. The address space allocation logic is modified to place a marker indicating a TLB purge in the queue of free address space blocks. Whenever the marker rises to the head of the queue a TLB purge is issued. Task dispatches at all other times do not require TLB purging.

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P. M. Gannon et al., "Apparatus and a Method for TLB Purge Reduction in a Multi-Level Machine System", U.S. Application Ser. No. 08/112,174 filed Aug. 26, 1993.

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