Electricity: power supply or regulation systems – Self-regulating – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2000-12-22
2002-10-01
Berhane, Adolf Deneke (Department: 2838)
Electricity: power supply or regulation systems
Self-regulating
Using a three or more terminal semiconductive device as the...
C323S901000
Reexamination Certificate
active
06459249
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a reset circuit for deactivating a circuit configuration in the event that the supply voltage drops below a specific level to an undervoltage.
A reset circuit of the generic type serves for deactivating an external circuit configuration, e.g. in the form of a microcontroller circuit which is operated by a supply voltage and is intended to be brought to a stable, deactivated state if the supply voltage falls below a specific level, so that logic circuits operated in connection with the microcontroller circuit cannot assume undefined states. In other words, the external circuit configuration is deactivated.
Reset circuits according to the prior art operate, e.g. with a charge pump, which is fed by the supply voltage of the microcontroller, and with a transistor operating as an actuator, across which a bias voltage is dropped. The bias voltage can be kept very small by means of the charge pump during normal operation. In the case of undervoltage supply, the bias voltage assumes a relatively large value and thus reliably deactivates the microcontroller circuit if the supply voltage drops below a specific value. A hysteresis effect is produced in this case, so that the microcontroller circuit “starts up” again only if the supply voltage rises above a specific threshold value.
Circuits of the aforementioned type are relatively complex and expensive.
DE 195 27 603 A1 discloses an electrical circuit configuration for generating a reset signal in the case of undervoltage supply of a microcomputer, which circuit configuration has a series circuit—connected to a voltage to be monitored formed by an npn transistor and a resistor, at the junction point of which the reset signal can be tapped off. The resistor must have a relatively high resistance in order to keep the thermal loading on the transistor within limits. This resistor together with resistors which are located in the microcomputer and are connected to the positive pole of the voltage to be monitored forms a voltage divider, whereby an unambiguous reset signal (low signal) is not ensured.
EP 0 767 416 A1 discloses a circuit for supplying voltage to a microcomputer with generation of a reset signal in the case of undervoltage supply, which circuit has a plurality of capacitors. Undefined states, which should be avoided under all circumstances, can arise in the time between the undershooting of the minimum supply voltage and the appearance of a reset signal.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a reset circuit which overcomes the above-mentioned disadvantageous of the prior art circuits of this general type, and which operates reliably over a wide supply voltage range, requires few components and is thus cost-effective and simple to integrate.
With the foregoing and other objects in view there is provided, in accordance with the invention a reset circuit for, in an event of an undervoltage supply, deactivating a circuit configuration that is fed by a supply voltage. The reset circuit includes two active switching elements having forward paths connected together at a junction point and connected in series between a supply voltage and a ground reference potential. Each one of the two active switching elements has a control terminal. The reset circuit also includes a resistor having one terminal connected to the ground reference potential and another terminal connected to the junction point, at least one forward-biased diode; a first current source connected to the supply voltage via the at least one diode; and a second current source connected to the supply voltage. The control terminal of each one of the two active switching elements is driven by a respective one of the first current source and the second current source. The junction point provides a reset signal.
In accordance with an added feature of the invention, the active switching elements are transistors selected from the group consisting of bipolar transistors and field-effect transistors.
In accordance with an additional feature of the invention, the reset circuit includes a current mirror circuit which includes one of the two active switching elements. The one of the two active switching elements has a drain-source path connected between the supply voltage and the junction point. The one of the two active switching elements is driven by the first current source. The current mirror circuit also includes another active switching element having a drain-source path connected between the first current source and the ground reference potential, the other active switching element being driven by the first current source.
In accordance with another feature of the invention, the reset signal is active low.
In accordance with a further feature of the invention, the reset circuit is used with a motor vehicle electronic circuit.
In accordance with a concomitant feature of the invention, the second current source is directly connected to the supply voltage.
The reset circuit according to the invention has the advantage that a minimum number of components are required and deactivation of the external circuit configuration is performed reliably.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a reset circuit, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 4011484 (1977-03-01), Paice et al.
patent: 5070295 (1991-12-01), Morigami
patent: 5359233 (1994-10-01), Mumper et al.
patent: 5552725 (1996-09-01), Ray et al.
patent: 6163183 (2000-12-01), Azimi et al.
patent: 195 27 603 (1996-02-01), None
patent: 0 374 968 (1990-06-01), None
patent: 0 562 397 (1993-09-01), None
patent: 0 595 748 (1994-05-01), None
patent: 0 767 416 (1997-04-01), None
Published International Application No. WO 98/05126 (Sandhu), dated Feb. 5, 1998.
Swart Marten
Wagner Ekkehart-Peter
Zelger Christian
Berhane Adolf Deneke
Greenberg Laurence A.
Locher Ralph E.
Siemens Aktiengesellschaft
Stemer Werner H.
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