Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2001-02-28
2002-12-31
Nelms, David (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
C365S226000, C327S530000
Reexamination Certificate
active
06501671
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a semiconductor memory device which enables selective production of different semiconductor memory devices operating at different external power-supply voltages.
2. Description of the Background Art
General-purpose DRAMs (Dynamic Random Access Memory), that have been wide spread as semiconductor memory devices, include SDR (Single Data Rate)-SDRAMs (synchronous-DRAMs), each of which transmits data, an address signal and a control signal to/from an external source in synchronization with a rise of an external clock, and DDR (Double Data Rate)-SDRAMs, each of which transmits data, an address signal and a control signal to/from an external source in synchronization with both the rise and a fall of the external clock. The DDR-SDRAMs have been made to attain improved performance by making a transfer rate thereof twice as fast as that of the SDR-SDRAMs.
An SDR-SDRAM is different from a DDR-SDRAM not only in the transfer rate of data or the like, but also in a power-supply voltage and an interface. Currently, the power-supply voltage and a power-supply voltage for output of the SDR-SDRAM are 3.3V and the interface is LVTTL (Low Voltage-TTL) for 3.3V. On the other hand, the power-supply voltage and the power-supply voltage for output of the DDR-SDRAM is 2.5V, and the interface is SSTL-2 (Stub Series Terminated Logic) for 2.5V.
With development of high-density DRAMs, a semiconductor process has come to involve more miniaturization process, and thus a break-down voltage of a gate oxide film of an MOS transistor has been reduced. This requires reduction of an operating voltage in order to attain higher reliability of the DRAMs. However, a personal computer as a main application product of the DRAMs utilizes, in a system with one standard, a plurality of generations of DRAMs, making it difficult to reduce the operation voltage of DRAM. Thus, in order to address the problem described above, a voltage down converter is provided within a chip in a DRAM, for an example, to reduce an external power-supply voltage of 3.3V to an internal power-supply voltage of 2.5V. As a result, the SDR-SDRAM is supplied with the external power-supply voltage of 3.3V, and is operated at the internal power-supply voltage of 2.5V which is down-converted from the external power-supply voltage of 3.3V by the voltage down converter. The DDR-SDRAM is supplied with the external power-supply; voltage of 2.5V to be operated.
It is then necessary to produce different products with different power-supply voltages for the SDR-SDRAMs and for the DDR SDRAMs when DRAMs are produced, while both of the SDR-SDRAM and the DDR-SDRAM are around in the market.
Though an SDR-SDRAM and a DDR-SDRAM are different in their interfaces, many parts in memory cores are common. Thus, a semiconductor memory device can be designed, in consideration of its productivity, such that an SDR-SDRAM and a DDR-SDRAM can be selectively produced, for example, by simply replacing a metal mask. An internal circuit of the SDRAM is divided into three parts as follows: (1) a part usable for both SDR and DDR, (2) a part used only for SDR, and (3) a part used only for DDR. When the SDR-SDRAM is to be produced, (2) the part used only for SDR is activated and (3) the part used only for DDR is inactivated. When, on the other hand, the DDR-SDRAM is to-be produced, (2) the part used only for SDR is inactivated and (3) the part used only for DDR is activated.
Thus, as shown in
FIG. 19
, a semiconductor memory device
500
enabling selective production of the SDR-SDRAM and the DDR-SDRAM includes a switch
120
, a common circuit
130
, exclusive circuits
140
and
150
, an external power-supply line
160
, an internal power-supply line
170
, a power-supply line
180
and a voltage down converter
190
.
When the DDR-SDRAM operated at the external power-supply voltage of 2.5V is to be produced, switch
120
is connected to external power-supply line
160
by a metal mask, and when the SDR-SDRAM operated at the internal power-supply voltage of 2.5V which has been down-converted from the external power-supply voltage of 3.3V is to be produced, it is connected to internal power-supply line
170
by the metal mask. Common circuit
130
is connected to power-supply line
180
and is operated at the external power-supply voltage of 2.5V and the internal power-supply voltage of 2.5V which has been down-converted from the external power-supply voltage of 3.3V. Exclusive circuit
140
is connected to internal power-supply line
170
and is operated at the internal power-supply voltage of 2.5V only when the external power-supply voltage of 3.3V is supplied thereto. Exclusive circuit
150
is connected to external power-supply line
160
and is operated only at the external power-supply voltage-of 2.5V.
External power-supply line
160
supplies the external power-supply voltage of 2.5V or 3.3V to switch
120
, exclusive circuit
150
and voltage down converter
190
. Internal power-supply line
170
is connected to voltage down converter
190
to supply the internal power-supply voltage of 2.5V which has been down-converted by voltage down converter
190
to switch
120
and exclusive circuit
140
.
Voltage down converter
190
down-converts the external power-supply voltage of 3.3V, supplied from external power-supply line
160
, to the internal power-supply voltage of 2.5V.
When external power-supply line
160
is supplied with the external power-supply voltage of 3.3V, i.e., when the SDR-SDRAM is produced, voltage down converter
190
down-converts the external power-supply voltage of 3.3V to the internal power-supply voltage of 2.5V, and supplies the down-converted voltage to internal power-supply line
170
. Switch
120
is connected to internal power-supply line
170
by the metal mask. Then, common circuit
130
and exclusive circuit
140
are supplied with the internal power-supply voltage, and common circuit
130
inputs/outputs various signals to/from exclusive circuit
140
, for writing and reading data. Exclusive circuit
150
operated only at the external power-supply voltage of 2.5V is then inactivated by an inactivation signal from common circuit
130
, and is supplied with the external power-supply voltage of 3.3V by external power-supply line
160
.
On the other hand, when external power-supply line
160
is supplied with the external power-supply voltage of 2.5V, i.e., when the DDR-SDRAM is produced, internal power-supply line
170
to which exclusive circuit
140
is connected is further connected to external power-supply line
160
by a switch (not shown), and exclusive circuit
140
is supplied with the external power-supply voltage of 2.5V. Further, switch
120
is connected to external power-supply line
160
. Then, common circuit
130
and exclusive circuit
150
are supplied with the external power-supply voltage of 2.5V. Common circuit
130
inputs/outputs various signals to/from exclusive circuit
150
for reading and writing data. Exclusive circuit
140
operated only at the external power-supply voltage of 3.3V is inactivated by an inactivation signal from common circuit
130
.
However, if a signal of a level H (logical high) is output from common circuit
130
to exclusive circuit
150
in order to inactivate exclusive circuit
150
when SDR-SDRAM is to be produced, current disadvantageously flows through from external power-supply line
160
to a ground terminal (such current is hereinafter referred to as “through current”) in exclusive circuit
150
, making it impossible to produce a semiconductor memory device with low power consumption.
Referring to
FIG. 20
, common circuit
130
includes an inverter
135
provided between a power-supply node
133
and a ground terminal
134
. Inverter
135
includes a P-channel MOS transistor
131
and an N-channel MOS transistor
132
. In inverter
135
, a signal of a level L (logical low) is input from a node N
20
and a signal of level H is output to a node N
21
. Power-
McDermott & Will & Emery
Nelms David
Yoha Connie C.
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