Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-05-19
2002-11-26
Sherry, Michael J. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB, C714S700000
Reexamination Certificate
active
06486693
ABSTRACT:
This invention relates generally to automatic test equipment and more specifically to the testing of integrated circuit chips that output clocks for timing.
In the manufacture of integrated circuit chips, the chips are generally tested at least once. The test results are used in various ways. They can be used to separate good chips from faulty chips. They can also be used to grade parts. For example, chips are usually rated by the maximum speed at which they can operate or by the amount of the data they can store, with the chips having a higher speed or larger memories being sold at higher prices. Often, variations in the chip manufacturing process result in some chips operating at a higher speed or having more usable memory. The test results allow the parts that have greater capabilities to be graded for sale at a higher price. In some cases, defects on chips can be repaired using laser repair stations or similar equipment. Another way that test results might be used in the manufacture of chips is to guide the repair of chips.
To test parts in a manufacturing setting, automatic test equipment (sometimes called a “tester”) is used. Traditional automatic test equipment contains numerous “channels” or “pins.” A channel is a circuit that can generate or measure a single digital signal. To test a chip, each lead of the chip is connected to a channel on the tester. Each channel is controlled by a clock within the tester. For each period of the tester clock, each channel can generate or measure the signal.
The channel circuitry is often highly programmable so that the automatic test equipment can simulate virtually any kind of input to the chip or detect whether an expected output, regardless of the format of the output, was produced. In addition to accepting programming inputs that define the shape of the signal that is generated or measured, the channel circuitry can also be programmed to generate or check for an expected signal at a precise time.
When the chips are used to make electronic systems, such as a computer, an error in the time when a signal is produced can be just as disruptive as a signal of the wrong value or form. Most chips are clocked, meaning that they have a clock input that changes state on a periodic basis. The chip latches a set of input signals at a set time in relation to the change of state of the clock signal. If valid data signals are not applied to the chip at this time, the chip will latch improper data and therefore the computer will likely malfunction. In a computer, the outputs of one chip are connected to the inputs of another. If the first chip does not produce output signals at the appropriate time relative to a clock input, the next chip receives its inputs at an incorrect time relative to the clock.
Traditionally, a common clock was used for every chip inside an electronic system. By having each chip produce its outputs and latch its inputs at certain times in relation to the common clock, it could be assured that valid data would be latched.
A problem arises in designing systems with common clocks. As signals move from one part of a system to another, some get slowed down more than others. As a result, signals that ought to occur at the same time often wind up occurring at different times. These time differences are sometimes called “skew.” When designing a system, skew must be taken into account. Even though valid data is expected to arrive at a chip at a certain time, the designer should design the system to wait until the maximum possible skew time after the data is expected before it latches the data. Having to wait this time reduces the number of processing operations the computer can perform in a second and is therefore undesirable.
More recently, new clocking architectures have been used in systems that need to process many operations per second. These architectures are sometimes referred to by the terms “source synchronous,” “clock forwarding” or “echo clocks,” all of which are generally synonymous. In these architectures, each chip producing output signals also produces an output clock signal that is fed to the chips that need to latch the output signals as inputs. The data clocks are derived from the common clock so that all chips in the system are operating at the same speed. However, the system still works even if the data clock and the common clock are not synchronized.
Because the data clock and the data signals are generated by the same chip and travel over similar paths, there is less skew between the data signals and the data clock than between the data signals and the common clock. Consequently, latching data signals based on the data clock wastes less time waiting to latch signals. U.S. Pat. No. 5,774,001 is an example of such a system.
However, testing chips made for source synchronous systems can be a problem. In testing parts with a common clock system, the tester can generate a signal to use as a common clock that has a set timing relationship to the tester clock. Channels measuring the data signals can operate at set times relative to the tester clock so that the time relationship between these measurements and the signal being used as the common clock would be known.
However, we have recognized a difficulty in testing chips made for a source synchronous system using conventional test equipment. Measurement times need to be tied to the data clock output by the chip under test rather than to a signal generated by the tester. Timing the measurement of the data values is a problem because the data clock runs to a different tester channel than the data signals. Additionally, the relative timings between the data signals and the data clock tend to exhibit jitter. To control the time at which the data signals were measured, the data clock would somehow have to be routed from its channel to a control input of each channel receiving a data signal associated with that clock. But, by the time the data clock signal could travel this distance, it would no longer have the required time relationship to the data signals. Thus, an improved method for testing source synchronous parts is required.
SUMMARY OF THE INVENTION
With the foregoing background in mind, it is an object of the invention to provide a test system that can accurately test parts made for source synchronous systems.
The foregoing and other objects are achieved in a test system having a fanout circuit very close to the device under test. The fanout circuit has an input connected to the data clock of the device under test and outputs connected to channel circuits in the tester that receive data from the device under test. These channel circuits use the data clock to strobe inputs. Different connection materials are used to interconnect the data clock and data signals to the tester.
In a preferred embodiment, coax with a low dielectric constant core is used to connect the data clock to the tester and a higher dielectric constant core coax is used to connect the data channels.
REFERENCES:
patent: 4792932 (1988-12-01), Bowhers et al.
patent: 5794175 (1998-08-01), Conner
Conner George
Reichert Peter
Kreisman Lance M.
Patel Paresh
Sherry Michael J.
Teradyne, Inc.
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