Trench isolated semiconductor device

Details Trench isolated semiconductor device Trench isolated semiconductor device

1999-12-22

2002-02-12

Meier, Stephen D. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S545000

Reexamination Certificate

active

06346736

ABSTRACT:

The present invention relates to a semiconductor device having a trench-isolated structure and, more particularly, to a method of reducing the capacitance between the wiring and substrate of the semiconductor device.
As higher-density and increasingly miniaturized semiconductor devices have been implemented in recent years, repeated attempts have been made to substitute a trench isolation technique for a LOCOS technique which is most prevalently used to form isolation for providing insulation between individual elements of the semiconductor devices. In accordance with the trench isolation technique, an insulating material is filled in a trench formed in a semiconductor substrate to form isolation.
Since planarization of a surface of a semiconductor substrate including the insulating material filled in the trench is important to the trench isolation technique, chemical mechanical polishing (CMP) has been used as a planarizing technique which achieves excellent in-plane uniformity free from pattern dependence. In the case where the trench occupies a large area in a CMP process for planarization, the provision of dummy island semiconductor portions has been proposed to avoid trouble resulting from so-called pattern dependence, which causes polishing properties to vary depending on the area of a region to be planarized. In other words, the trench is divided into a plurality of narrow trenches so that the surface of the semiconductor substrate is exposed between the individual trenches to form the dummy semiconductor portions which do not serve as active regions.
FIG. 19
shows an example of the conventional trench-isolated semiconductor device having the dummy island semiconductor portions.
As shown in
FIG. 19
, an active region
6
of a P-type silicon substrate
1
is formed with: a gate oxide film
2
; a gate electrode
4
made of a polysilicon film; and source/drain regions
5
into which an impurity has been introduced. An isolation region
7
surrounding the active region
6
is formed with a plurality of trench portions
8
each filled with a silicon oxide film. Between the individual trench portions
8
, there are provided semiconductor portions
9
having top surfaces at the same level as the top surfaces of the trench portions
8
. On the trench portions
8
also, there is provided a polysilicon wire
10
formed simultaneously with the gate oxide film
2
and the gate electrode
4
of an element. An interlayer insulating film
12
is deposited over the entire surface of the substrate, followed by a metal wire
13
provided thereon.
In this case, if the trench portions have such large widths as shown in FIG.
21
(
b
), a silicon oxide film filled in each of the trench portions is polished during the CMP process for planarizing the whole substrate so that the surface thereof is depressed due to pattern dependence, which leads to the trouble of degraded planarity or the like. The isolation structure as shown in
FIG. 19
has been proposed to prevent such trouble resulting from pattern dependence.
FIGS.
20
(
a
) to
20
(
g
) are cross-sectional views illustrating a process of manufacturing the conventional trench-isolated semiconductor device having an NMOS transistor.
In the step shown in FIG.
20
(
a
), a thin silicon oxide film
21
having a thickness of 10 nm and a silicon nitride film
22
are formed sequentially on the P-type silicon substrate
1
.
In the step shown in FIG.
20
(
b
), a plurality of trenches
14
each having a given width are formed in the silicon substrate
1
. However, the trenches
14
include: trenches
14
a
formed to surround the active region
6
to be formed with the element; trenches
14
b
formed in the isolation region
7
separated from the active region
6
by the trenches
14
a
to eliminate pattern dependence from planarity obtained at the completion of the manufacturing process; and trenches
14
c
for forming the polysilicon wires. In the isolation region
7
also, the semiconductor portions
9
have been provided to form at least one projecting portion surrounded by the trenches
14
. The semiconductor portions
9
may be considered as dummy active regions which do not function as active regions.
In the step shown in FIG.
20
(
c
), a silicon oxide film
23
is deposited over the entire surface of the substrate to fill in the trenches
14
.
In the step shown in FIG.
20
(
d
), the silicon oxide film
23
is polished by a CMP method. Subsequently, the silicon nitride film
22
and the silicon oxide film
21
are removed selectively to form the plurality of buried trench portions
8
each filled with the silicon oxide film and having a planarized surface. The buried trench portions
8
include: buried trench portions
8
a
functioning as isolation; buried trench portions
8
b
forming the dummy semiconductor portions
9
; and buried trench portions
8
c
for providing insulation between the polysilicon wires and the silicon substrate.
In the step shown in FIG.
20
(
e
), there are formed the gate oxide film
2
, the gate electrode
4
having sidewalls
24
on the side faces thereof, and the polysilicon wire
10
by using a known technique. The gate electrode
4
and the polysilicon wire
10
are formed simultaneously.
In the step shown in FIG.
20
(
f
), arsenic ions
25
are implanted into the active region
6
of the NMOSFET region by using a resist mask Rem covering the PMOSFET region and the isolation region to form the source/drain regions
5
. The NMOSFET is formed by the foregoing process steps.
In the step shown in FIG.
20
(
g
), the silicon oxide film is deposited to form the interlayer insulating film
12
, followed by the metal wire
13
formed thereon.
In the foregoing step shown in FIG.
20
(
f
), ions of such an impurity as phosphorus or arsenic have been implanted into the gate electrode
4
and source/drain regions
5
of the active region
6
in the step shown in FIG.
20
(
f
). However, impurity ions are not implanted in principle in the region other than the active region
6
, though they may be introduced slightly extensively into the periphery of the isolation region in considerations of mask displacement. Hence, impurity ions are not implanted in the dummy semiconductor portions
9
between the individual trench portions
8
.
A description will be given to the wiring-to-substrate capacitance of the trench-isolated semiconductor device having the small trench portions
8
which are discretely located and the dummy semiconductor portions
9
as shown in FIG.
19
and in a semiconductor device having a wide isolating/insulating film such as a LOCOS film. FIG.
21
(
a
) is a cross-sectional view for illustrating, by way of example, the wiring-to-substrate capacitance in the isolation region
7
having the dummy semiconductor portions
9
. FIG.
21
(
b
) is a cross-sectional view for illustrating the wiring-to-substrate capacitance of the semiconductor device having a LOCOS isolation film
100
and no dummy semiconductor portion. It is assumed here that impurity ions have not been implanted in the isolation region
7
during the implantation of ions into the source/drain regions and that the area occupied by the whole isolation region
7
is equal in each of the two semiconductor devices.
In the semiconductor device shown in FIG.
21
(
a
), a total wiring-to-substrate capacitance Cat corresponds to the sum of capacitances Ca
1
and Ca
2
, which is represented by the following equation (1):
Cat=&Sgr;Ca
1
+&Sgr;
Ca
2
  (1).
In the case where a member interposed between the wiring and substrate is composed of a homogeneous material, the wiring-to-substrate capacitance per unit area is inversely proportional to the distance between the wiring and substrate, so that the capacitance is larger as the distance is shorter. If the total wiring-to-substrate of the semiconductor device shown in FIG.
21
(
b
) is represented by Cbt when the dimension Da
2
shown in FIG.
21
(
a
) is equal to the dimension Dbt shown in FIG.
21
(
b
), the following inequality (2) is satisfied:
Cat>Cbt
  (2),
whic

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