Nonvolatile semiconductor storage device

Details Nonvolatile semiconductor storage device Nonvolatile semiconductor storage device

2001-06-14

2002-08-20

Ho, Hoai V. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185220

Reexamination Certificate

active

06438035

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to nonvolatile semiconductor storage devices and, in particular, to a nonvolatile semiconductor storage device that can achieve improved accuracy of read operation and verify operation during rewrite.
In recent years, a large-capacity flash memory has been developed for the markets of memory cards and files. For the above uses, the flash memory is required to have high-speed read and high-speed rewrite functions at a high density and a reduced cost.
As a nonvolatile semiconductor storage device having the above-mentioned functions, there has been proposed a read/rewrite circuit construction of a NAND type flash memory by Symposium on VLSI Circuits Digest of Technical Papers pp. 20-21, 1992.
FIG. 11
shows the construction of the read/rewrite circuit of the above-mentioned NAND type flash memory.
This circuit has an open bit line structure with one centered read/write circuit
111
, and verify circuits
112
and
113
are connected to each of the bit lines BLai and BLbi. The read/write circuit
111
operates as a flip-flop type sense amplifier in the read operation and the verify operation during rewrite and as a data latch circuit in the write operation. The control gate of a memory cell
204
is connected to an identical word line for every cell to be concurrently subjected to write.
Herein is mainly provided a description of the read operation and the verify operation during rewrite related to the present invention. In order to set the threshold voltage of the memory cell to a specified value in the write operation (or the erase operation), this verify operation during rewrite is to alternately execute the applying of a write pulse (or an erase pulse) and the verify operation. This verify operation during rewrite is basically the same as the read operation, while the threshold voltage value to be detected is changed.
The timing chart of
FIG. 12
shows the timing of the read operation in the aforementioned NAND type flash memory. The timing chart of
FIG. 12
shows an example in which the memory cell array (a) side is selected and the memory cell
204
is selected and subjected to read. A power voltage Vcc is assumed to be 3 V.
First of all, a voltage of ⅗ Vcc (1.8 V) is applied to a terminal Va, and a voltage of ½ Vcc (1.5 V) is applied to a terminal Vb.
Both control signals &phgr;pa and &phgr;pb to the gates of the transistors Tr
1
and Tr
2
have High level, and therefore, the transistors Tr
1
and Tr
2
are in the ON state. Accordingly, the potential of a selected bit line BLai is precharged with the voltage of ⅗ Vcc. On the other hand, the potential of a non-selected bit line BLbi, which is used as a dummy bit line for the open bit line system, is precharged with a voltage of ½ Vcc.
Then, the transistors Tr
1
and Tr
2
are put into the OFF state as shown in a period of t
1
to t
2
in FIG.
12
. Subsequently, by making both control signals SG
1
and SG
2
to the gates of select transistors S
1
and S
2
have High level, both the transistors S
1
and S
2
are put into the ON state. Then, non-selected word lines CG
1
through CG
3
and CG
5
through CG
8
are set to the Vcc level, while a word line CG
4
connected to the control gate of the selected memory cell
204
(to be subjected to read) is set to 0 V. In this stage, if the threshold voltage of the selected memory cell
204
is lower than 0 V (when the data of the memory cell
204
is “0”), then a current flows through the memory cell
204
. Other memory cells having control gates (CG
1
through CG
3
and CG
5
through CG
8
) to which the power voltage Vcc is applied are put into a state in which a cell current flows.
As described above, the current flows through the memory cell connected continuously to the memory cell
204
, and therefore, the potential of the selected bit line BLai reduces to ½ Vcc level or less as indicated by the potential waveform “0”-read of the bit line BLai shown in FIG.
12
and continues to reduce.
Conversely, when the threshold voltage of the selected memory cell
204
is higher than 0 V (data of the memory cell
204
represents “1”), no cell current flows through the memory cell
204
. Therefore, no current flows through the memory cell
204
even if the power voltage Vcc is applied to the control gates CG
1
, CG
2
, CG
3
and CG
5
through CG
8
of other memory cells. Therefore, the potential of the selected bit line BLai does not reduce as indicated by the potential waveform “1”-read of BLai shown in
FIG. 12
, and ⅗ Vcc level is maintained. On the other hand, since no cell current flows as described above, the potential of the non-selected bit line BLbi, which is used as a dummy bit line here, maintains the ½ Vcc level.
When the threshold voltage of this memory cell
204
is lower than 0 V, the select transistors S
1
and S
2
are put in the OFF state and the non-selected word lines CG
1
through CG
3
and CG
5
through CG
8
are set to 0 V in accordance with a timing at which the potential of the selected bit line BLai sufficiently reduces and becomes 0 V as shown in a period of t
2
to t
3
(potential waveform “0”-read) in FIG.
12
.
According to the description provided by way of example in
FIGS. 11 and 12
, the timing at which the potential reaches 0 V is merely of the operation of the memory cells
204
connected to the bit line BLai. However, even in the case of another memory cell or a memory cell connected to another bit line, the above-mentioned timing is the timing at which the selected bit line comes to have a voltage of 0 V when the data of the selected memory cell represents “0”.
Subsequently, both transistors TR
3
and TR
4
are put in the OFF state by control signals &phgr;p and &phgr;n to the gates of the transistors TR
3
and TR
4
provided on the power source side of the read/write circuit
111
in a period of t
4
to t
5
through the stable period of t
3
through t
4
in the circuit state shown in FIG.
12
. By this operation, the read/write circuit
111
is reset and put into a floating state.
Subsequently, the control signal &phgr;e is made to have High level to turn on the transistors Tr
5
and Tr
6
and set (equalize) the potentials of a node a and a node b to a voltage of ½ Vcc. When this equalization is ended as in the period of t
5
through t
6
of
FIG. 12
, the control signal &phgr;e is set to 0 V to set back the transistors Tr
5
and Tr
6
to the OFF state.
When the transistors Tr
7
and Tr
8
are put in the ON state by making the clock signals &phgr;a and &phgr;b have High level, the bit line BLai is connected to the node a, and the bit line BLbi is connected to the node b.
By this operation, when the data of the memory cell
204
represents “0”, the bit line BLai of a potential of 0 V and the node a of the potential of ½ Vcc are connected to each other, and the potential of the node a starts to reduce from ½ Vcc to 0 V. When the data of the memory cell
204
represents “1”, the bit line BLai of the potential of ⅗ Vcc and the node a of the potential of ½ Vcc are connected to each other, and the potential of the node a starts to increase from ½ Vcc to ⅗ Vcc.
The non-selected bit line BLbi of the potential of ½ Vcc is also connected to the node b of the potential of ½ Vcc, and therefore, the potential of the node b maintains the potential of ½ Vcc (period of t
6
to t
7
of FIG.
12
).
Subsequently, the transistor Tr
4
provided on the ground voltage side of the read/write circuit
111
is turned on in a period subsequent to t
7
of
FIG. 12
, and the transistor Tr
3
provided on the power source Vrw side is subsequently turned on.
At this time, the potential of the node b is ½ Vcc. When the data of the memory cell
204
represents “1”, the potential of the node a is higher than the voltage of ½ Vcc. Conversely, when the data of the memory cell
204
represents “0”, the potential is lower than the voltage of ½ Vcc. Therefore, when the data of the memory cell

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