Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2001-11-05
2002-08-27
Vu, Bao Q. (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
C323S272000, C323S283000
Reexamination Certificate
active
06441598
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to synchronous rectifier circuits, and more particularly to “buck”, “boost” and other switching voltage converter circuits (i.e., voltage regulator circuits) that include synchronous rectifier circuits, and still more particularly to such voltage converter circuits which operate with reduced power dissipation and improved efficiency.
FIG. 1
shows a conventional buck switching voltage converter
1
that includes a synchronous rectifier. The synchronous rectifier includes a large, low-resistance MOS N-channel transistor M
2
having its source connected to a ground conductor
3
, its gate being coupled by logic circuitry
14
to the output of a comparator
12
having its (+) input connected to a ground conductor
3
and its (−) input connected by conductor
5
to the drain of transistor M
2
. Logic circuitry
14
typically includes a latch circuit that prevents comparator
12
from turning transistor M
2
on more than once during each switching cycle. This can occur if the offset of comparator
12
is negative and causes transistor M
2
to be turned off “early”, in which case the magnitude of the V
DS
voltage between the drain and source of transistor M
2
rapidly increases to equal the forward bias voltage of a “body diode” D and then decreases back down to the threshold voltage of comparator
12
. Transistor M
2
inherently includes the drain-to-substrate body diode D, with its N-type cathode region common with the drain and its P-type anode connected to the source of transistor M
2
.
Voltage converter circuit
1
also includes an input conductor
2
receiving an unregulated voltage Vin and applying it to the drain of an N-channel switching transistor M
1
. The source of transistor M
1
is connected by conductor
5
to the drain of transistor M
2
and to a first terminal of an inductor
6
having an inductance L. A second terminal of inductor
6
is connected by an output conductor
7
to a first terminal of a load or output capacitor
8
having a capacitance C. As is well known to those skilled in the art, an inductor current I
INDUCTOR
flows back and forth between inductor
6
and capacitor
8
during operation of voltage converter circuit
1
. The second terminal of load capacitor
8
is connected to ground conductor
3
. A regulated output voltage Vout is produced on output conductor
7
. The regulated output voltage Vout is applied to an input of a feedback control circuit
19
that compares Vout with a reference voltage and accordingly produces a signal on conductor
4
to control the switching of transistor M
1
so as to cause voltage regulator circuit
1
to maintain the desired regulated value of Vout.
In any integrated circuit manufacturing process, the comparator (such as comparator
12
FIG. 1
) has an inherent offset voltage, which may be positive or negative. The value of the comparator offset voltage produced by any particular integrated circuit manufacturing process has a statistical distribution.
In operation, switching transistor M
1
is turned on during the initial part of each switching cycle. This causes current to flow from the source of the unregulated voltage Vin through transistor M
1
and inductor
6
such that conductor
7
supplies current to maintain the desired value of output voltage Vout across a load capacitor
8
that may be connected to conductor
7
and/or across any additional external load that may be connected to conductor
7
. During this portion of the switching cycle, the voltage of conductor
5
is high, so the output of comparator
12
is at a logical “0” level. The low “
0
” output voltage produced by comparator
12
causes logic circuit
14
to keep transistor M
2
turned off. The flow of I
INDUCTOR
into load capacitor
8
increases the value of Vout to the desired regulated value determined by a reference voltage within feedback control circuit
19
, which then produces a signal on conductor
4
that abruptly turns switching transistor M
1
off.
The current I
INDUCTOR
cannot change abruptly, and therefore continues to flow from conductor
5
through inductor
6
and conductor
7
. This causes the voltage on conductor
5
to rapidly decrease to a level approximately 600 millivolts below ground, at which point body diode D becomes forward biased enough to supply the current I
INDUCTOR
. The low voltage on conductor
5
causes comparator
12
to switch, causing it to produce a high logical “1” output level. That causes logic circuit
14
to produce a high voltage level on the gate of transistor M
2
after a short delay, turning transistor M
2
on.
The size of transistor M
2
is selected so that when it is turned on, its channel resistance (Ron) is low enough that its drain-to-source voltage V
DS
is reduced from the approximately 600 millivolt forward bias voltage of body diode D to only approximately 100 millivolts (which reverse biases body diode D). Therefore, the power dissipation due to the flow of I
INDUCTOR
through transistor M
2
after it is turned on is much lower than the power dissipation due to the flow of I
INDUCTOR
through body diode D before transistor M
2
is turned on. After transistor M
1
is turned off, the magnitude of I
INDUCTOR
gradually decreases at the rated (I
INDUCTOR
)/dt=Vout/L. Therefore, the drain-source voltage V
DS
voltage of transistor M
2
decreases at roughly the same rate as I
INDUCTOR
until the V
DS
of transistor M
2
is equal to the offset voltage of comparator
12
, which typically can be as large as approximately 10 millivolts above or below ground.
Typically, the size of transistor M
2
is chosen so that when the maximum value of I
INDUCTOR
is flowing through the channel resistance of transistor M
2
, its V
DS
voltage is approximately equal to the above mentioned 100 millivolts. The 10 millivolt offset voltage of comparator
12
typically corresponds to roughly 10 percent of the maximum value of I
INDUCTOR
. If, for example, the magnitude of the offset voltage of comparator
12
is 10 millivolts, the decreasing V
DS
voltage causes comparator
12
to turn off transistor M
2
either too soon or too late, depending on whether the offset voltage is positive or negative. In either case, the power dissipation is substantially increased. If the offset voltage is negative, transistor M
2
is turned off too late, and then it draws current from load capacitor
8
and any additional load that is connected to output conductor
7
. Even if the net current flow out of conductor
7
to an external load (not shown) is zero, I
INDUCTOR
at that time has a value equal to approximately 10 percent of the maximum current through inductor
6
and oscillates between inductor
6
and load capacitor
8
, and also flows through the channel resistance of transistor M
2
and dissipates power therein.
If the comparator offset voltage is positive, then transistor M
2
will be turned off too soon. In that case, there is still up to approximately 10 percent of the maximum inductor current still flowing in inductor
6
, and it flows through the large 600 millivolt forward bias voltage of body diode D, and consequently dissipates a large amount of power.
Thus, the prior art buck voltage converter
1
of
FIG. 1
is characterized by decreased conversion efficiency for either positive or negative offset voltages of comparator
12
.
Synchronous rectifier circuits of the kind described above also can be used in motor control circuits, class D audio amplifiers, and other circuitry.
Thus, there is an unmet need for an improved synchronous rectifier that accomplishes improved conversion efficiency when used in a utilization circuit such as an integrated circuit voltage converter, a motor control circuit, a class D audio amplifier, or the like.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an improved synchronous rectifier circuit having reduced power dissipation when used in conjunction with a utilization circuit.
It is another object of the present invention to provide an improved synchronous
Brady W. James
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Vu Bao Q.
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