Current driver configuration for MRAM

Details Current driver configuration for MRAM Current driver configuration for MRAM

2001-07-03

2002-11-19

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S158000, C365S173000

Reexamination Certificate

active

06483768

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a current driver configuration for an MRAM (magnetoresistive random access memory) including a memory cell array having a plurality of memory cells at crossover points between word lines and bit lines and including drivers which are assigned to the word lines and the bit lines and are in each case provided at one end of the word lines and the bit lines.
It is known that the magnetically variable electrical resistance of the individual memory cells in MRAMs is utilized for the memory effect. As is shown in
FIG. 2
, such a memory cell is formed at the crossover between a word line WL, which is assumed to be an upper conductor LTO here, and a bit line BL, which is formed by a lower conductor LTU. At the crossover point between these two conductors LTO and LTU, a specific multilayer system is present between the two conductors LTO and LTU. This multilayer system includes a hard-magnetic material layer HML and a soft-magnetic material layer WML, between which there is a tunnel oxide film TL. In other words, the hard-magnetic material layer HML, the tunnel oxide film TL and the soft-magnetic material layer WML are stacked, one on top of the other, on the lower conductor LTU. The soft-magnetic material layer WML being covered on its top side by the upper conductor LTO.
The configuration of the soft-magnetic material layer WML and hard-magnetic material layer HML can, if appropriate, also be interchanged, with the result that the hard-magnetic material layer HML is provided “at the top”, while the soft-magnetic material layer WML is situated on the lower conductor LTU. Equally, it is possible to provide the upper conductor LTO for the bit line BL and the lower conductor LTU for the word line WL.
All that is important is that the tunnel oxide film TL is provided between the soft-magnetic material layer WML and the hard-magnetic material layer HML, these two layers WML and HML respectively being assigned to an upper conductor LTO and a lower conductor LTU. Instead of an oxide, another material can also be used for the tunnel oxide film.
The thickness d
TL
(cf.
FIG. 3
) of the tunnel oxide film TL may preferably be in the range from 0.5 to 5 nm. The thickness d
WML
of the soft-magnetic material layer WML and the thickness d
HML
of the hard-magnetic material layer HML lie approximately in the range from 1 to 5 nm. In principle, however, thicknesses that deviate therefrom are also permissible.
In this way, the multilayer system including the soft-magnetic material layer WML, the tunnel oxide film TL and the hard-magnetic material layer HML forms a memory cell with a resistor R between the upper conductor LTO and the lower conductor LTU, resulting in the configuration shown diagrammatically in FIG.
4
.
The resistance of the multilayer system, that is to say of the memory cell, between the conductors LTO and LTU or between the word line WL and the bit line BL depends, then, on whether the magnetization direction in the two material layers WML and HML runs in a manner oriented parallel or antiparallel with respect to one another. If the magnetization directions in the two material layers WML and HML are oriented parallel to one another, then the resistor R has a low resistance, whereas in the case of an antiparallel orientation of the magnetization of these material layers, a high resistance of the resistor R can be recorded. Since the hard-magnetic material layer HML has a fixed magnetization, the memory cell is written to by switching the soft-magnetic material layer, by applying a corresponding magnetic field to the material layer. This magnetic field is generated by superposition of the two magnetic fields which are formed by a current I
o
in the upper conductor LTO and a current I
u
in the lower conductor LTU. In other words, by sending corresponding currents I
o
, and I
u
, in a specific direction through the conductors LTO and LTU, respectively, it is possible to switch over the magnetization direction in the soft-magnetic material layer WML, with the result that this is oriented parallel or antiparallel with respect to the magnetization direction of the hard-magnetic material layer HML. Antiparallel-oriented magnetizations of the two material layers WML and HML are assumed in the example of
FIG. 3
, this being indicated by corresponding arrows, so that the resistor R has a high resistance in this case.
When switching the soft-magnetic material layer WML between antiparallel- and parallel-oriented magnetizations with respect to the hard-magnetic material layer HML, and vice versa, it should be noted that the soft-magnetic material of the layer WML has a hysteresis property. The triggering of the switching operation requires the superposition of the magnetic fields which are generated by the currents I
o
, and I
u
in the upper conductor LTO and in the lower conductor LTU, respectively. For a switching operation, it is necessary to reverse the original current direction of the current I
o
, and of the current I
u
, respectively.
In a conventional DRAM, the word lines are each connected to the gate terminals of switching transistors, with the result that the capacitances formed by the gate terminals are also applied to the word lines. This means that a voltage for rapidly reversing the charge of the capacitances for each word line has to be provided in each case by a driver. The drivers of DRAMs include n- and p-channel field-effect transistors so that low and high voltages can be switched without any losses. However, in order to obtain the same driver power for a p-channel field-effect transistor as for an n-channel field-effect transistor, due to the lesser charge carrier mobility in a p-channel field-effect transistor, it is necessary to specify for the latter a channel width approximately 2.5 times that for the n-channel field-effect transistor.
A conventional driver for the word lines of a DRAM (dynamic random access memory) or FeRAM (ferroelectric random access memory) having a p-channel field-effect transistor P
1
and an n-channel field-effect transistor NO, which are connected in series between a driver voltage DRV and ground and are connected to a read-out terminal RDOUTn by their gate terminals, is shown in FIG.
5
. The word line WL is located at the junction point between these two transistors P
1
and N
0
. The channel width wp of the p-channel field-effect transistor P
1
is 2.5 times the channel width wn of the n-channel field-effect transistor N
0
.
In an MRAM, in contrast to a DRAM, a high current of 2.5 to 3 mA is required for writing, but the voltage across the individual memory cells should be as small as possible in order to avoid breakdowns of the tunnel oxide layer. By way of example, if a tunnel oxide layer thickness d
TL
of 2 nm or less is assumed, then the voltage across the tunnel oxide film should not exceed 0.5 V so that a service life of 10 years can be achieved.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a current driver configuration which overcomes the above-mentioned disadvantages of the heretofore-known current driver configurations of this general type and which can provide small voltages with high currents and which, at the same time, requires only a small area.
With the foregoing and other objects in view there is provided, in accordance with the invention, in combination with an MRAM having a memory cell array with a plurality of memory cells, word lines, and bit lines, the word lines and the bit lines having respective first ends and having respective second ends opposite the respective first ends, the word lines and the bit lines crossing one another at respective crossover points, the memory cells being disposed at the crossover points, a current driver configuration which includes:
drivers assigned to respective ones of the word lines and the bit lines, the drivers being provided at the respective first ends of the word lines and the bit lines;
the drivers each including a first n-channel field-effect transistor a

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