Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Ball or nail head type contact – lead – or bond
Reexamination Certificate
1999-10-08
2002-02-05
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Ball or nail head type contact, lead, or bond
C257S780000, C438S613000, C438S614000
Reexamination Certificate
active
06344695
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device to be mounted on a main circuit board and a process for manufacturing the same.
2. Description of the Related Art
One example known in the prior art of such a semiconductor device as described above is illustrated in FIG.
14
.
In this semiconductor device, conductive inner bumps
20
of a smaller diameter, each projected from an electrode (not shown) provided on an active surface of a semiconductor chip
10
, are electrically connected to connection terminals
32
provided on the upper surface of a sub-circuit board
30
having substantially the same size as that of the semiconductor chip
10
. A gap between the semiconductor chip
10
and the sub-circuit board
30
is filled with underfiller
40
so that the semiconductor chip
10
is bonded to the sub-circuit board
30
. Conductive pads
34
are provided on the lower surface of the sub-circuit board
30
. The conductive pads
34
are electrically connected via circuit patterns (not shown) of the sub-circuit board
30
to connecting terminals
32
on the upper surface of the sub-circuit board
30
. A conductive outer bump
60
of a larger diameter having a hemispherical shape is projected from each of the conductive pads
34
for the electrical connection to a connection terminal
52
on the upper surface of a main circuit board
50
.
According to this semiconductor device, it is possible to electrically connect a plurality of electrodes of various kinds formed at a small pitch in the peripheral region of the active surface of the semiconductor chip
10
, via the inner bumps
20
and the circuit patterns of the sub-circuit board
30
, with a plurality of conductor pads
34
provided on the lower surface of the sub-circuit board
30
at a large pitch in a matrix manner. And, it is possible to replace a plurality of electrodes arranged at a small pitch in the peripheral region of the active surface of the semiconductor chip
10
for the electrical connection to the connection terminals
52
on the upper surface of the main circuit board
50
, with the conductive pads
34
arranged at a large pitch on the lower surface of the sub-circuit board
30
in a matrix manner. Together therewith, it is also possible to electrically connect selected electrodes formed on the active surface of the semiconductor chip
10
to each other via circuit patterns of the sub-circuit board
30
.
It is possible to form a generally semispherical outer bump
60
of a larger diameter on each of the conductive pads
34
arranged at a large pitch in a matrix manner or the like, while maintaining a predetermined distance from the other outer bump
60
to avoid the contact with the other outer bumps
60
formed on the adjacent conductor pads
34
. Then the plurality of generally hemispherical outer bumps
60
of a larger diameter could be easily and assuredly electrically connected to the plurality of connection terminals
52
arranged on the upper surface of the main circuit board
50
at a larger pitch in a matrix manner or the like. Thus, it is possible to electrically connect the plurality of electrodes on the active surface of the semiconductor chip
10
to the respective connection terminals
52
on the upper surface of the main circuit board
50
corresponding thereto.
The above-described known semiconductor device, however, has a drawback in that the semiconductor chip
10
is mounted on the main circuit board
50
via the sub-circuit board
30
having a larger occupation volume, resulting in the increase in size of the semiconductor device.
Further, the production thereof is troublesome because the semiconductor chip
10
must be bonded to the circuit board
30
via the underfiller
40
.
Also, since the sub-circuit board
30
is complicated in structure, the production cost of the semiconductor device increases.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device capable of eliminating such a problem in the prior art, which has no sub-circuit board to minimize a size thereof and reduce the production cost, and a process for manufacturing the same.
According to the present invention, there is provided a semiconductor device comprising: a semiconductor chip having an electrode and also having an active surface covered with an insulating layer; a rewiring circuit formed on the insulating layer, the rewiring circuit electrically connected to the electrode; an inner bump formed on a conductive pad which is a part of the rewiring circuit; an insulating film attached to the rewiring circuit and a surface of the insulating layer at a peripheral portion of the rewiring circuit, the insulating film having a through hole into which the inner bump is inserted; and an outer bump superimposed on the inner bump in the through hole so as to project to an outside opposite to the semiconductor chip.
The through hole is tapered so that cross-section area thereof is gradually larger toward the outside.
The outer bump is made of an eutectic solder, such as composed of 63 weight % of Sn and 37 weight % of Pb.
According to another aspect of the present invention, there is provided a semiconductor device comprising; a semiconductor chip having an electrode and also having an active surface covered with an insulating layer; a rewiring circuit formed on the insulating layer, the rewiring circuit electrically connected to the electrode; a conductive pad formed as a part of the rewiring circuit; an insulating film attached to the rewiring circuit and a surface of the insulating layer at a peripheral portion of the rewiring circuit, the insulating film having a through hole so that the conductive pad is exposed in the through hole; and an outer bump superimposed on the conductive pad in the through hole so as to project to an outside opposite to the semiconductor chip.
According to still another aspect of the present invention, there is provided a process for manufacturing a semiconductor device, the process comprising the following steps of: covering an active surface of a semiconductor chip with an insulating layer; forming a rewiring circuit on the insulating layer so that the rewiring circuit is electrically connected to an electrode of the semiconductor chip; forming an inner bump of a high melting point material on a conductive pad which is a part of the rewiring circuit; attaching an insulating film to the rewiring circuit and a surface of the insulating layer at a peripheral portion of the rewiring circuit, the insulating film having a through hole into which the inner bump is inserted; and superimposing an outer bump on the inner bump in the through hole so as to project to an outside opposite to the semiconductor chip.
According to still another aspect of the present invention, there is provided a process for manufacturing a semiconductor device, the process comprising the following steps of: covering an active surface of a semiconductor chip with an insulating layer; forming a rewiring circuit on the insulating layer so that the rewiring circuit is electrically connected to an electrode of the semiconductor chip; forming a conductive pad formed as a part of the rewiring circuit; attaching an insulating film to the rewiring circuit and a surface of the insulating layer at a peripheral portion of the rewiring circuit, the insulating film having a through hole so that the conductive pad is exposed in the through hole; and superimposing an outer bump on the conductive pad in the through hole so as to project to an outside opposite to the semiconductor chip.
REFERENCES:
patent: 5019673 (1991-05-01), Juskey et al.
patent: 5668399 (1997-09-01), Cronin et al.
patent: 5740956 (1998-04-01), Seo et al.
patent: 5943597 (1999-08-01), Kleffner et al.
patent: 5977632 (1999-11-01), Beddingfield
patent: 6198169 (2001-03-01), Kobayashi et al.
patent: 40 25 622 (1992-02-01), None
patent: 196 28 702 (1997-01-01), None
patent: 0 810 649 (1997-12-01), None
patent: 4-256343 (1992-09-01), None
Powell et al., “Flip-Chip on FR-4 Integra
Shinko Electric Industries Co. Ltd.
Staas & Halsey , LLP
LandOfFree
Semiconductor device to be mounted on main circuit board and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device to be mounted on main circuit board and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device to be mounted on main circuit board and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2939444