Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays
Reexamination Certificate
2000-09-20
2002-10-15
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
C365S201000, C365S233100
Reexamination Certificate
active
06465817
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a digital camera comprising the same, and more specifically, it relates to a semiconductor integrated circuit having a large-scale macro cell part such as a CPU and a digital camera comprising the same.
2. Description of the Prior Art
A semiconductor integrated circuit forming a logic circuit responsive to the specification of a target system (e.g., a digital camera) around a core of a large-scale macro cell part such as a CPU on a single semiconductor substrate is well known in general.
An ASIC (application specific integrated circuit) readily implementing a device for a specific application with CAD (computer aided design) is generally known as a method employed for forming the aforementioned semiconductor integrated circuit. As to a method of designing such an ASIC, a gate array system, a standard cell system and an embedded array system are generally known as methods of efficiently designing semi-custom LSIs.
In the gate array system, basic cells covered with transistors in an arrayed manner are provided and wired for forming a logic circuit. The gate array system requires only a wiring step as the fabrication step, and hence a TAT (turnaround time) between completion of design and trial manufacture of a sample is advantageously reduced.
However, a large-scale macro cell part such as a CPU or a memory cannot be formed by the gate array system.
On the other hand, such a large-scale macro cell part can be readily implemented by the standard cell system. In the standard cell system, optimally designed verified logic circuit cells and a macro cell part are previously registered in a CAD database and arbitrarily combined with each other through CAD. However, this standard cell system employs a mask specific to a type from a transistor forming step, and hence fabrication cannot be started until the design is completed. In the standard cell system, therefore, the TAT is inconveniently lengthened as compared with the gate array system.
To this end, there is proposed the embedded array system having a structure embedding a macro cell part of standard cells in a random logic part of a gate array. The embedded array system adopts advantages of the gate array system and the standard cell system. After deciding the number of gates of the random logic part and the type of the embedded macro cell part, fabrication of a wafer is immediately started to advance fabrication of the embedded array up to a stage preceding a wiring step. Completion of logical design is waited in this state. After termination of a logic simulation, an LSI is completed by simply wiring the random logic part.
In the embedded array system, the macro cell part of the standard cells is previously registered and hence parts other than the macro cell part are designed. Therefore, the macro cell part of the standard cells may not be embodied to a transistor unit level and hence the TAT can be reduced for the standard cells. Further, circuits forming the random logic part can be changed only through the wiring step.
When the overall semiconductor integrated circuit is wired in the aforementioned conventional embedded array system, the macro cell part is treated as a black box having only an input/output port and a power supply port connected to the macro cell part and boundary information indicating the magnitude of the macro cell part as pattern information. In other words, the random logic part is wired/designed on the basis of only the boundary information indicating the magnitude of the macro cell part regardless of detailed information on the inner part of the macro cell part in the conventional embedded array system, in order to reduce the quantity of data. When wires are provided on the macro cell part of the standard cells for wiring the random logic part, therefore, these wires may come into contact with and short to internal wires of the macro cell part.
In general, therefore, a macro cell part
153
must be regarded as an inhibit area for wires
152
of a random logic part
151
when wiring the random logic part
151
as shown in
FIG. 12
, so that the wires
152
bypass the macro cell part
153
. Consequently, wiring efficiency is disadvantageously reduced around the macro cell part
153
to hinder improvement in degree of integration. Further, the wiring length of the wires
152
is increased to increase wiring capacity. Thus, the semiconductor integrated circuit is disadvantageously inhibited from speeding up its operations.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor integrated circuit capable of improving the degree of integration and speeding up its operations.
Another object of the present invention is to reduce the wiring length of a logic part of a semiconductor integrated circuit thereby reducing wiring capacity.
Still another object of the present invention is to provide a digital camera having the aforementioned semiconductor integrated circuit.
A semiconductor integrated circuit according to an aspect of the present invention comprises a macro cell part and a logic part formed around the macro cell part. The macro cell part includes a logic wiring region for receiving a wire provided in the logic part.
In the semiconductor integrated circuit according to this aspect, the macro cell part is formed to include the logic wiring region for receiving the wire provided in the logic part, whereby the wire in the logic part can be provided in the macro cell part. Thus, such a probability that the wire of the logic part must bypass the macro cell part can be reduced. Therefore, the wiring length of the wire provided in the logic part is so reduced that wiring capacity can be reduced while the wire can be prevented from congestion around the macro cell part. Consequently, circuit operations can be speeded up while the degree of integration of the semiconductor integrated circuit can be improved.
In the semiconductor integrated circuit according to this aspect, the logic wiring region of the macro cell part preferably includes a region substantially provided with no internal wire of the macro cell part. Thus, the wire of the logic part will not come into contact with the internal wire of the macro cell part when the same is provided on the logic wiring region of the macro cell part. The logic wiring region of the macro cell part may include a region provided with an internal wire of the macro cell part to an extent not hindering provision of the wire of the logic part. Also in this case, the wire of the logic part can be provided on the logic wiring region of the macro cell part.
In the semiconductor integrated circuit according to this aspect, the logic wiring region of the macro cell part is preferably provided on a peripheral portion of the macro cell part. The internal wire of the macro cell part tends to congest rather on a central portion than on the peripheral portion. When providing the logic wiring region on the peripheral portion of the macro cell part in the aforementioned manner, therefore, the macro cell part can be readily designed. In this case, the logic wiring region is preferably provided on a corner portion, an upper edge portion and a lower edge portion of the macro cell part. Alternatively, the logic wiring region may be provided along a peripheral portion of the macro cell part over the whole area of the peripheral portion. Further alternatively, the logic wiring region may be provided on a corner portion and both side edge portions of the macro cell part.
In the semiconductor integrated circuit according to this aspect, the logic wiring region of the macro cell part may be provided on a central portion of the macro cell part in the form of a strip.
In the semiconductor integrated circuit according to this aspect, each of the macro cell part and the logic part preferably has a multilayer wiring structure, and the logic wiring region is preferably formed on at least one layer of the macro cell part. When the macro cell
Sanyo Electric Co,. Ltd.
Tran Mai-Huong
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