Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1996-04-23
2002-02-19
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S503000, C257S920000
Reexamination Certificate
active
06348723
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and in particular a semiconductor device including an insulation gate type field effect transistor.
2. Description of the Related Art
Conventionally, any wiring layer in a semiconductor device is provided on a chip formed on a semiconductor substrate with a thick interlayer insulation film interposed therebetween. The wiring layer may consist of one layer or a plurality of layers.
FIGS. 3A
to
3
C are diagrams describing the general structure of a conventional semiconductor device. Specifically, FIGS
3
A to
3
C show a wiring portion of a semiconductor device formed by a process that employs, for example, one polysilicon layer and one metal layer.
FIG. 3A
is a plan view showing the wiring portion;
FIG. 3B
is a cross-sectional view taken at view IIIb—IIIb in
FIG. 3A
; and
FIG. 3C
is a circuit diagram showing a buffer circuit composed of the wiring shown in FIG.
3
A and invertors.
As shown in
FIG. 3B
, an insulation film
106
is formed on the surface of a semiconductor substrate
104
. On the substrate
104
, wires
101
and
102
are formed with the insulation film
106
and an interlayer insulation film
105
interposed therebetween. The wire
101
serves as a signal wire through which a signal is transmitted. The wire
102
is connected to ground. In this specification, the wire
102
is referred to as a “grounding wire.” The wires
101
and
102
are formed by patterning an aluminum layer formed on the interlayer insulation film
105
. Therefore, in a portion where the wires
101
and
102
intersect each other, the wires must be rearranged so that one wire is located above the other so as to interpose the interlayer insulation film
105
.
In this conventional example, the wire
101
is disrupted at both sides of the wires
102
. The disrupted ends of the wire
101
are connected to a polysilicon wire
103
via contact holes
103
a
, the polysilicon wire
103
being formed below the wire
101
with the interlayer insulation film
105
interposed therebetween. The polysilicon wire
103
is formed by patterning a polysilicon layer formed on the insulation film
106
. The polysilicon wire
103
is formed concurrently with the gates of transistors, etc. The wire
103
, which is formed by thus patterning the polysilicon layer, is insulated from the wires
101
and
102
(formed by patterning the above-mentioned aluminum layer) by the interlayer insulation film
105
.
Thus, it is ensured that the signal wire
101
and the grounding wire
102
(formed of the patterned aluminum layer) intersect each other in a three-dimensional manner by reconnecting the signal wire
101
to the underlying polysilicon wire
103
.
FIG. 3C
is a circuit diagram showing a buffer circuit composed of the wires shown in FIG.
3
A and invertors
110
and
111
. As shown in
FIG. 3C
, the preceding invertor
110
and the subsequent invertor
111
are interconnected with each other via the above-described signal wire
101
. A wiring resistance
107
of the polysilicon wire
103
is present between the invertors
110
and
111
.
Since the portion of the signal wire
101
which is composed of the polysilicon wire
103
intersects the grounding wire
102
, the signal wire
101
has a parasitic capacitance
108
formed between the polysilicon wire
103
and the aluminum layer functioning as the grounding wire
102
and a parasitic capacitance
109
formed between the polysilicon wire
103
and the semiconductor substrate
104
.
FIG. 4
shows a simulated result of the conventional buffer circuit shown in FIG.
3
C. By inputting an input signal B
1
to the preceding invertor
110
, an output signal B
2
is obtained from an output node thereof. However, the output signal B
2
, which corresponds to the input signal B
1
, is rounded at the output node of the invertor
110
, i.e., an input node of the subsequent invertor
111
, as shown in FIG.
4
. As a result, the waveform of an output signal B
3
of the subsequent invertor
111
is delayed with respect to the waveform of the input signal B
1
.
In an attempt to manufacture semiconductor devices at low cost, semiconductor devices are further miniaturized and the manufacturing processes thereof are simplified, thereby reducing the amount of time required for the production of semiconductor devices. This has resulted in a trend to reduce the thickness of LOCOS layers and films between wire layers (interlayer insulation films). In the structure shown in
FIG. 3B
, for example, the thicknesses of the interlayer insulation film
105
between the polysilicon wire
103
and the aluminum layer
102
(functioning as the grounding wire) and the insulation film
106
between the polysilicon wire
103
and the semiconductor substrate
104
are to be reduced. However, this results in an increase in the parasitic capacitance which accompanies the signal wire, thereby increasing the delay of signals in such signal wires interconnecting various circuits. As a result, this hinders high-speed signal processing of the device.
In general, the delay time of a signal is determined by the driving ability of a buffer and a time constant, which is a product obtained by multiplying the wiring resistance by the wiring capacitance.
In the circuit configuration shown in
FIG. 3C
, the delay time of the output signal B
3
corresponding to the input signal B
1
is determined by a time constant obtained by multiplying the value of the wiring resistance
107
and the sum of the values of the parasitic capacitances
108
and
109
. Assuming that the thickness of the film between the wire layers is reduced by one-half by employing a process for further miniaturization, which does not effect the driving ability of the buffer and the values of the wiring resistance
107
, the value of the sum of the parasitic capacitances
108
and
109
doubles (because the thickness of the film between the wire layers has been reduced by one-half). The value of the wiring resistance
107
is not changed. As a result, the time constant, which determines the signal delay time, also doubles. Thus, under the condition that the buffer has the same driving ability, the signal delay time doubles by reducing the thickness of the film between the wire layers.
SUMMARY OF THE INVENTION
A semiconductor device according to the present invention includes: a semiconductor substrate; a signal wire, disposed on the semiconductor substrate; for transmitting a signal between circuits; and a dummy wire disposed between the signal wire and a region of the semiconductor substrate to form a parasitic capacitance with the signal wire, wherein a signal, which has the same phase as a phase of a signal supplied to the signal wire, is supplied to the dummy wire.
In one embodiment of the invention, the circuits include at least one transistor including a semiconductor layer, and the signal wire includes a semiconductor portion which is formed simultaneously with the semiconductor layer of at least one transistor.
In another embodiment of the invention, the dummy wire includes an impurity diffusion region formed in a surface of the semiconductor substrate to oppose the semiconductor portion of the signal wire.
In still another embodiment of the invention, the signal wire includes a first conductive portion with an insulating layer interposed between the first conductive portion and the semiconductor portion of the signal wire, the semiconductor portion being electrically connected to the first conductive portion through a first contact hole formed in the insulating layer.
In still another embodiment of the invention, the dummy wire includes a second conductive portion with the insulating layer interposed between the second conductive portion and the impurity diffusion region of the dummy wire, the impurity diffusion region being electrically connected to the second conductive portion through a second contact hole formed in the insulating layer.
In still another embodiment of the invention, the semiconductor device further inc
Chaudhuri Olik
Nixon & Vanderhye P.C.
Sharp Kabushiki Kaisha
Weiss Howard
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