Polar analog-to-digital converter

Details Polar analog-to-digital converter Polar analog-to-digital converter

2000-10-25

2002-10-15

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C375S308000, C370S313000

Reexamination Certificate

active

06466150

ABSTRACT:

BACKGROUND OF THE INVENTION
I. Field of the Invention
The present invention relates to electronic circuits. More particularly, the present invention relates to a novel and improved polar analog-to-digital converter (ADC).
II. Description of the Related Art
An analog-to-digital converter is an important component in many electronic circuits. An ADC converts a continuous analog signal into quantized samples at discrete time intervals. The samples are subsequently processed by other digital signal processing blocks to derive the desired data.
ADCs are commonly used in communication systems that employ various modulation schemes such as amplitude modulation (AM), frequency modulation (FM), and phase modulation (PM). As the names of these modulation schemes imply, the information is encoded in the amplitude, frequency, or phase of a carrier signal. The PM scheme includes several variants such as phase shift keying (PSK), binary PSK (BPQK), quadrature PSK (QPSK), offset QPSK (OQPK), m-ary PSK (m-PSK), and others. Other modulation schemes are also commonly used, such as quadrature amplitude modulation (QAM) which is a combination of the AM and PM schemes.
Phase and frequency modulations are employed in many digital communications systems, examples of which include code division multiple access (CDMA) communications systems, television transmission systems, broadcast systems, paging systems, and others. At a transmitter, data is processed, encoded, modulated using one of the modulation schemes noted above (e.g. FM or PM), and transmitted. At a receiver, the signal is received, conditioned, and demodulated into baseband signals (or possibly a low intermediate frequency (IF) signal) in a manner complementary to that used at the transmitter. The baseband signals typically include an inphase (I) signal and a quadrature (Q) signal. Conventionally, the I and Q signals are sampled with two ADCs to generate inphase and quadrature samples that are further processed to extract the phase or frequency information. Such processing may be accomplished with a look-up table, an angle calculation algorithm, or other techniques.
Many conventional receivers use two ADCs to sample the I and Q signals. The ADCs are typically designed with a (relatively) large number of bits of resolution to handle variations in the amplitude of the signals and to provide the accuracy required by the angle calculation algorithm. These high-resolution ADCs can be complex to design, costly to implement, and may further consume a large amount of power.
For many applications, since the information is embedded in the phase or frequency of a carrier signal, a “polar” ADC that provides phase information directly is highly desirable. It is also highly desirable that the polar ADC be simple to implement and consumes little power.
SUMMARY OF THE INVENTION
The present invention provides a polar analog-to-digital converter (ADC) that can be advantageously used to extract phase and/or frequency information from a pair of input signals. A typical I-Q plane is partitioned into M sectors by M/2 lines that intersect at the center of the I-Q plane. M/2 comparators are used to determine whether the input signals fall on one side or the other of each line. Simple decoding circuitry is then used to determine the phase of the input signal based on the comparison results from the comparators. The polar ADC can provide more accurate phase determination since scaled signals are compared, without quantization. Moreover, the polar ADC requires less circuitry to implement than a conventional linear ADC.
An embodiment of the invention provides a polar ADC that includes first and second scaling elements, a number of comparators, and a decoder. The first scaling element receives and scales a first signal to provide a set of one or more scaled first signals. The second scaling element receives and scales a second signal to provide a set of one or more scaled second signals. Each of the comparators receives and compares a respective pair of scaled first and second signals and provides a comparison output. The decoder receives the comparison outputs from the comparators and generates output data, which can be indicative of the phase and/or frequency of the first and second signals. The polar ADC can be advantageously implemented using C-MOS circuits that operate on differential current signals. In a specific implementation, each scaling element includes first through fourth current mirror circuits. The first current mirror circuit receives an input signal via a reference path and provides one or more scaled signals via a first set of mirror paths, where the input signal corresponds to either the first or second signal. The second current mirror circuit receives a complementary input signal via a reference path and provides one or more scaled signals via a second set of mirror paths. The third current mirror circuit receives, via a reference path, a scaled signal from one mirror path of the first current mirror circuit and provides one or more scaled signals via a third set of mirror paths. And the fourth current mirror circuit receives, via a reference path, a scaled signal from one mirror path of the second current mirror circuit and provides one or more scaled signals via a fourth set of mirror paths. The first and second sets of mirror paths provide sinking current, and the third and fourth sets of mirror paths provide sourcing current.
In a specific implementation, each comparator is implemented as a current comparator that receives a respective input current signal generated by combining current signals corresponding to selected ones of the scaled first and second signals. The current comparator can include first and second transistors and an inverter. The first and second transistors couple together at their sources and their bases. The inverter has an input coupled to the sources of the transistors and an output coupled to the gates of the transistors. The decoder can be implemented with a look-up table or combinatory logic.
Another embodiment of the invention provides a receiver that includes a front end unit, a demodulator, first and second filters, and a polar ADC. The front end unit receives a modulated signal and provides an intermediate signal. The demodulator receives and demodulates the intermediate signal with a set of inphase and quadrature carrier signals to generate demodulated inphase and quadrature signals, respectively. The first and second filters respectively receive and filter the demodulated inphase and quadrature signals to provide filtered inphase and quadrature signals. The polar ADC receives the filtered inphase and quadrature signals and generates output data. The polar ADC can be implemented as described above and can be configured to perform phase and/or frequency demodulation of the received signal.
Yet another embodiment of the invention provides a method for determining phase or frequency information in a received signal. In accordance with the method, a first signal and a second signal are received. Each of the received first and second signals is scaled with one or more scaling coefficients to generate a set of scaled signals. Pairs of scaled first and second signals are then generated, and the signals in each pair are compared to provide a comparison result. The comparison results for the pairs of scaled signals are decoded to generate output data. The scaling and pairing are dependent on the M/2 lines that define an M-sector polar ADC. For M equal sectors, the first and second signals can be scaled with scaling coefficients defined above.


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