Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
2001-03-05
2002-12-31
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C257S693000, C257S777000, C257S779000
Reexamination Certificate
active
06501173
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an MCP (Multi-Chip Package) semiconductor disk device capable of expanding memory and to a semiconductor device with provisions to facilitate testing a plurality of chips accommodated in an MCP (Multi-Chip Package).
As demands are growing for higher integration density of semiconductor devices mounted on a printed circuit board, the packages of semiconductor devices are getting smaller. In recent years, a variety of kinds of CSPs (chip size packages), a general reference to packages equal to or slightly larger than the chip size, have been developed. (The CSP package type is classified as a derivative of the existing packages.) They are making large contributions to reducing size and weight of portable terminals.
At the same time, since the speed at which the memory capacity required by the system devices increases is higher than the speed at which the memory integration improves, a three-dimensional mounting of a memory has been proposed as a means to increase the memory capacity while minimizing an increase in the memory mounting area. The applicant of this invention developed a technology of DDP (Double Density Package) in which an LOC (Lead On Chip) structure is formed in layers to double the memory capacity of a package with the same external size as the 1-mm-thick surface mount package TSOP (see JP-A-11-163255, laid open on Jun. 18, 1999, corresponding to U.S. patent application Ser. No. 09/161,725 filed on Sep. 29, 1998). This publication discloses a 128 MDRAM-DDP, in which LOC structure (64 MDRAM) lead frames are stacked in layers and sealed with a mold, with the leads bonded.
Unlike a conventional magnetic disk device, a semiconductor disk device using a flash memory has no mechanical moving parts, and thus is unlikely to have erroneous operations and failures due to physical impacts. It has the advantages of being smaller in device size and able to make a faster read/write access to data than in the conventional magnetic disk device. The semiconductor disk device has conventionally been realized as a memory board or memory card having a plurality of flash memories and a controller that controls the flash memories. In this case, the plurality of flash memories are realized as discrete LSIs and the controller is also realized as one LSI.
To deal with the aforementioned problem that a large number of parts in the semiconductor disk device makes the size reduction difficult, JP-A-6-250799, laid open on Sep. 9, 1994, discloses a semiconductor disk device in which a flash memory unit, an interface with external devices, and a controller unit are integrated in a single LSI. The semiconductor disk device of a one-semiconductor-chip configuration has an expansion memory interface which, when the user wishes to expand the flash memory built into the chip, allows the storage capacity of the semiconductor disk device to be increased, as required, by the user externally connecting a flash memory one chip at a time.
JP-A-11-86546, laid open on Mar. 30, 1999, discloses a technology whereby a logic chip and a memory chip, fabricated separately, are mounted parallelly and sealed in one package. Further, JP-A-11-19370 (corresponding to U.S. patent application Ser. No. 09/450,676, filed on Nov. 30, 1999) shows an example structure of MCP.
SUMMARY OF THE INVENTION
The inventors of this invention studied a semiconductor disk device suited for incorporation into various portable information terminals (palm size PC, handy terminal, etc.) and digital cameras as main products to which the invention can be applied. The specifications require the semiconductor disk device to have the smallest possible mounting area, weight and power consumption. A controller is available in a variety of kinds for various applications. For security reasons, the controller is expected to have its specification updated frequently, so that it is important to shorten the development period of new package products to reduce cost—the common priority among the commercial products.
When a semiconductor disk device disclosed in JP-A-6-250799 is to be manufactured in a single semiconductor chip configuration, i.e., in the form of a system LSI, the following problems may arise: (1) there is a need to develop a new process, which in turn increases the number of processes, leading to an increase in cost; (2) when all the constitutional units are manufactured by the same process, the performances of the individual units may become worse than when the individual units are fabricated in the dedicated processes; (3) redesigning the entire chip as a result of changes in the specifications of the controller unit is not advantageous in terms of reducing the development cost and shortening the development TAT; and (4) because the constitutional units are arranged two-dimensionally, the size becomes large for a single chip.
In the LSI incorporated into a single package by arranging a plurality of chips parallelly as described in JP-A-11-86546, the reduction in the mounting area remains small to an extent that the mounting area is not smaller than the sum of the areas of the individual chips.
(1) A first object of the present invention is to propose a package configuration for the semiconductor disk device, which has a small mounting area to facilitate its incorporation into small portable information terminals, and which can cope quickly with type changes of the controller due to specification changes, reduce the development TAT (Turn Around Time: time spent from the material processing to the delivery of a product; or number of days from the start of development to the completion of development) and keep the development cost low.
Further, in a proposal to construct a semiconductor disk device in the MCP configuration, the inventors of this invention studied the problems experienced when conducting tests on a product incorporating a memory chip and a controller chip in a single package. The existing memory and controller (logic) are individually packaged and subjected to tests individually before being mounted on the printed circuit board. When combining two chips and forming them as a single package product, it is natural to conceive also bringing into the package the “wiring” that is on the printed circuit board between the memory and the controller. This, however, poses a problem in the testing that is conducted before shipping of the product. When the existing memory and controller are tested as individual single packages, the memory is tested by a memory tester and the controller is tested by a logic tester. These existing test environments, however, cannot be used under the same conditions as in the conventional tests if the memory and the controller are incorporated into one package and internally interconnected as described above. When for example the memory is tested by the memory tester, the influence (leakage current) due to internally connecting the controller cannot be precluded entirely, so that the identical test cannot be conducted under the conventional memory testing environment. The same can be said of the testing of the controller. That is, even if the influences of the internal connection is reduced as much as possible and an analysis considering these influences is performed, the equality of the test is expected to deteriorate.
Further, the memory tester and the logic tester have different characteristics. As the memory capacity increases, the test time also increases. To deal with this situation the memory tester enhances the test productivity by testing a large number of memories simultaneously. As for the logic tester, on the other hand, although it uses many signal terminals for applying a very large test pattern to the LSI being tested, the test time is generally about two orders of magnitude smaller than the memory test time. Because of this characteristic, the logic tester enhances the test productivity by increasing the rate at which the LSIs are mounted and tested. If a mixed tester having both of these test functions with different characte
Kanemoto Kouichi
Nishizawa Hirotaka
Antonelli Terry Stout & Kraus LLP
Nelms David
Nguyen Dao H.
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