Semiconductor memory device with a hierarchical word line...

Details Semiconductor memory device with a hierarchical word line... Semiconductor memory device with a hierarchical word line...

2002-03-25

2002-11-05

Tran, M. (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

Reexamination Certificate

active

06477105

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device having a divided word line structure in which word lines are divided into main word lines and sub-word lines. More specifically, the present invention relates to an arrangement for driving a sub-word line to a selected state.
2. Description of the Background Art
FIG. 11
is a schematic representation of a configuration of an array portion of a conventional semiconductor memory device. In
FIG. 11
, memory cells MC are arranged in a matrix of rows and columns. A sub-word line is provided correspondingly to each row of memory cells MC. Sub-word lines SWL
00
, SWL
01
, SWL
10
, SWL
11
are shown in FIG.
11
. Memory cells MC are divided into blocks along the row direction, and sub-word lines SWL are arranged in the respective blocks. A main word line ZMWL is provided in common to these sub-word lines. Sub-word line drivers SWD
00
, SWD
01
, SWD
10
, SWD
11
are provided to sub-word lines SWL
00
, SWL
01
, SWL
10
, SWL
11
, respectively. Each of these sub-word line drivers SWD
00
, SWD
01
, SWD
10
, SWD
11
drives a corresponding sub-word line to the selected state according to the signal potential on main word line ZMWL and a row select signal RSL. Row select signal RSL includes complementary signals SD and ZSD, and designates a sub-word line in a set of sub-word lines aligned in the column direction. Thus, row select signal RSL (sub-decode signals SD and ZSD) designates one of sub-word lines SWL
00
and SWL
10
, and one of sub-word lines SWL
01
and SWL
11
.
By providing one main word line ZMWL to a plurality of rows of memory cells, the pitch condition of main word line ZMWL is mitigated. Only the sub-word line drivers are connected to main word line ZMWL, and memory cells MC are not connected to main word line ZMWL. Thus, the load (impedance) on main word line ZMWL can be reduced, and the word line can be driven to the selected state at a high speed. Such an arrangement in which word lines are divided into main word lines ZMWL and sub-word lines SWL (generically indicating sub-word lines SWL
00
, SWL
01
, SWL
10
, SWL
11
) is referred to as a divided word line structure.
Moreover, a bit line pair BLP is shown in FIG.
11
. Bit line pair BLP includes complementary bit lines BL and /BL, and a memory cell MC is connected to one of bit lines BL and /BL.
FIG. 12
is a diagram representing a configuration of sub-word line driver SWD shown in FIG.
11
. Referring to
FIG. 12
, sub-word line driver SWD includes a P-channel MOS transistor Q
1
that is rendered conductive, when the signal potential on main word line ZMWL is at a ground voltage Vss level, to transmit a sub-decode signal SD onto sub-word line SWL, an N-channel MOS transistor Q
2
that is rendered conductive, when the signal potential on main word line ZMWL is at a high voltage Vpp, to drive sub-word line SWL to ground voltage Vss level, and an N-channel MOS transistor Q
3
that is rendered conductive, when sub-decode signal ZSD is at an array power-supply voltage Vdda level, to drive sub-word line SWL to ground voltage Vss level.
Sub-decode signal SD changes between high voltage Vpp and ground voltage Vss, and sub-decode signal ZSD changes between array power-supply voltage Vdda and ground voltage Vss. High voltage Vpp is transmitted to sub-word line SWL by sub-decode signal SD for the reason given below.
As shown in
FIG. 12
, a memory cell MC includes a memory capacitor MQ for storing information, and an access transistor MT rendered conductive in response to the signal potential on sub-word line SWL to connect memory capacitor MQ to bit line BL (or /BL). Access transistor MT is formed by an N-channel MOS transistor. Therefore, when writing into memory capacitor MQ logic high or “H” level (array power-supply voltage Vdda level) data, there is a need to prevent the voltage level of the “H” level data of memory capacitor MQ from being lowered by threshold voltage loss in access transistor MT. In order to compensate for the threshold voltage loss, high voltage Vpp higher than array power-supply voltage Vdda is transmitted on sub-word line SWL. In order to reliably set P-channel MOS transistor Q
1
to the off state, that main word line ZMWL is driven to high voltage Vpp level.
With the arrangement of sub-word line driver SWD shown in
FIG. 12
, MOS transistor Q
1
attains the off state while MOS transistor Q
2
attains the on state when main word line ZMWL is at high voltage Vpp level so that MOS transistor Q
2
drives sub-word line SWL to ground voltage Vss level regardless of the logic levels of sub-decode signals SD and ZSD. When main word line ZMWL is at high voltage Vpp level of the non-selected state, sub-word line SWL also is held at ground voltage Vss level of the non-selected state.
On the other hand, when main word line ZMWL is driven to ground voltage Vss level of the selected state, MOS transistor Q
1
attains either the off or on state while MOS transistor Q
2
attains the off state. When sub-decode signal SD is at high voltage Vpp level, MOS transistor Q
1
attains the on state so that the sub-decode signal of high voltage Vpp level is transmitted on sub-word line SWL. When sub-decode signal SD is at ground voltage Vss level of the non-selected state, MOS transistor Q
1
attains the off state, with its gate and its source being at the same voltage level. In this state, both MOS transistors Q
1
and Q
2
attain the off state. Sub-decode signal ZSD at this time is at array power-supply voltage Vdda level, and MOS transistor Q
3
attains the on state, driving sub-word line SWL to ground voltage Vss level. Thus, the use of complementary sub-decode signals SD and ZSD prevents sub-word line SWL from electrically floating.
FIG. 13
is a diagram representing a configuration of a conventional sub-decode signal generating portion. In
FIG. 13
, the sub-decode signal generating portion includes a sub-decoder
900
for generating a sub-decode fast signal ZSDF according to a predecode signal X, and a sub-decode signal generating circuit
910
for generating complementary sub-decode signals (word line designating signal) from sub-decode fast signal ZSDF.
Sub-decoder
900
includes a P-channel MOS transistor
901
connected between a high voltage node receiving a high voltage Vpp and a node
902
and receiving a reset signal ZRSET at a gate thereof, and an N-channel MOS transistor
903
connected between node
902
and a ground node and receiving predecode signal X at a gate thereof. Reset signal ZRSET changes between high voltage Vpp and ground voltage Vss. Predecode signal X changes between peripheral power-supply voltage Vddp and ground voltage Vss.
Sub-decode signal generating circuit
910
includes an inverter
911
for receiving sub-decode fast signal ZSDF to generate sub-decode signal SD, and an inverter
912
for receiving an output signal from inverter
911
to generate a complementary sub-decode signal ZSD. Inverter
911
receives high voltage Vpp as one operating power-supply voltage, while inverter
912
receives array power-supply voltage Vdda as one operating power-supply voltage. Therefore, sub-decode signal SD has an amplitude of high voltage Vpp, and the complementary sub-decode signal ZSD has an amplitude of array power-supply voltage Vdda. Now, the operation of the sub-decode signal generating portion shown in
FIG. 13
will be described.
At a standby state, reset signal ZRSET is at ground voltage Vss level and predecode signal X is also at ground voltage Vss level. Therefore, node
902
is charged to high voltage Vpp level by MOS transistor
901
in the on state.
Sub-decode signal SD attains the ground voltage level of the logic low or “L” level, and the complementary sub-decode signal ZSD attains array power-supply voltage Vdda level of the logic high or “H” level. Thus, in sub-word line driver SWD shown in
FIG. 12
, MOS transistor Q
3
is in the on state (and main word line ZMWL is at high voltage Vpp level), and sub-word line SWL is ma

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