Method for manufacturing non-volatile memory cell array

Details Method for manufacturing non-volatile memory cell array Method for manufacturing non-volatile memory cell array

2001-04-24

2002-11-19

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185300, C365S185330

Reexamination Certificate

active

06483751

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to a pre-erasing/erasing mechanism for flash EEPROM (Electrically Erasable and Programmable Read Only Memory) devices. The invention is particularly useful for flash arrays that utilize Negative Gate Channel Erase (NGCE) operations because it improves erase operations by reducing field intensity variations in tunnel oxides caused by processing deviations, increases the number of endurance cycles, and results in fewer over-erase errors.
BACKGROUND OF THE INVENTION
The endurance cycles of an EEPROM, especially the number of program and erase cycles, is the primary determinant of the life span of such device. Endurance cycles refer to the number of times which data can be reliably erased, re-programmed, and read back without errors. Accordingly, the number of endurance cycles dictates in large part the usable life of an EEPROM device. Consequently, one significant goal of prior art efforts is the maximization of such endurance cycles through the use of improved cell architectures which minimize cycle stress, as well as intelligent erase, program methods designed to be less stressful on the cell architecture.
Fowler-Nordheim (FN) tunneling is one of the most well-known, well-understood and prevalent techniques used in the art for erasing flash memory cells. A significant problem arises from the fact that certain cells (bits) in the memory array tend to be “fast” and others “slow” during an erase operation. In other words, because such cells tend to over-accumulate, or under-accumulate charge on their floating gates, or because charge becomes trapped in various locations, these cells tend to have threshold voltages that deviate significantly from a target threshold voltage. For this reason, when a “fast” cell is erased, it is much more likely to become over-erased. When a cell is over-erased during an erase operation, this causes additional administrative overhead, because it must be corrected if at all possible. This is undesirable, of course, because it slows down the operation of the device from being re-programmed with new data.
The existence of excess charge on the “fast” bits caused them to be over-erased for a couple of reasons. First, the FN erase mechanism depends strongly on the electrical field across the thin tunnel oxide layer in the flash cell; with more charge, the field is proportionately higher. This causes more charge to move off the floating gate during the erase operation. In other words, the fast bits have electrical field intensities that deviate significantly from desired target field strengths. Second, at the beginning of the FN erase, the floating gates are fully charged (i.e., in a programmed state) and the electrical field is a maximum. This means that the rate of erasure (the electrical discharge rate of the floating gate) is also highest at the onset of the FN erase operation. Thus, if fast bits are not corrected, they tend to become over-erased, and this leads to concomitant problems of excess leakage current and/or data errors. In the long run, these leaky bits cause failures, reduce endurance cycles, etc. As mentioned above, the problem is especially acute in (but not limited to) FN tunneling erase operations used with NGCE configurations. This is because the electrical field becomes extremely strong between the negative gate and the substrate well.
To date, there are very few practical solutions for dealing with this phenomenon, and no easy way known to applicants for compensating for electrical field intensity variations that occur in flash memory cell arrays. These field variations arise naturally both from wafer processing operations, which, by their nature, result in differences in cell structures, tunnel oxide characteristics (thickness and uniformity), etc., as well as from cycling of the device in normal operation. As the number of cells increase in EEPROM devices, and integration density increases, and cycling increases, the field variations also correspondingly increase because of the nature of normal distributions.
A related situation is addressed by U.S. Pat. No. 5,901,089, incorporated by reference herein. In this reference, the individual logic levels of a multi-bit cell are kept stable by ensuring that the threshold voltages of such cell are maintained within predefined threshold ranges. This is accomplished using what it refers to as “mini” erase/program operations, where a pulse is applied so that only enough charge is added or removed from a cell sufficient to keep it within a safe operating range for that state. While this approach is beneficial for improving sensing (read) operations, this technique does not appear to be very practical as a pre-erase conditioning operation. This is because it requires a significant amount of administrative overhead to perform this type of procedure on a cell by cell basis. Moreover, the reference is primarily directed ensuring that Vt overshoot is reduced for each programmed cell, and does not really address the issue of how to ensure that the behavior of cells collectively is relatively uniform and predictable during a subsequent operation in which they are to be transitioned from one logical level to another. In other words, there is no attempt made to treat one segment of the cell population (the “fast” cells) differently than another as may be necessary to achieve better operational results. Nor does this reference teach or suggest using a series of lesser strength erase signals to completely erase a programmed cell.
For these reasons, an effective method for dealing with so called fast bits is not known in the art, but is extremely desirable. Optimally, the erased set of cells has a relatively uniform distribution centered around a target erase value. To get this uniform distribution, however, it is necessary: (1) to place the cells in a similar state (initial floating gate voltage/electrical field); and (2) for them to have similar electrical discharge characteristics. The first step can be accomplished by a conventional programming step, which, in theory, is intended to add sufficient charge to put all the cells into an initial target programmed voltage threshold state V
p
. To date, nonetheless, applicants are unaware of specific and practical mechanisms for achieving the second step of controlling individual cell electrical discharge characteristics. To accomplish this goal, it is necessary to control the initial electric field at the tunneling oxide. If this electric field is not reduced at the onset of FN erasure for the fast bit segment of the array, the fast bits will be erased faster than average bits in the memory array. By the time the average bits are erased, the fast bits are already in a state of over-erasure. Correspondingly, if the electric field can be reduced at the beginning of the erasure for a particular bit, this will slow down the rate of erasure for the bit in question.
SUMMARY OF THE INVENTION
An object of the present invention, therefore, is to eliminate the problems generally inherent in the aforementioned FN tunneling erase operations when used with NGCE type EEPROM devices;
Another object of the present invention is to provide an improved circuit and method for erasing flash memory cells so that threshold voltage distributions of such cells are tightened both before and after an erase operation;
A further object of the present invention is to provide a circuit and method for pre-erasing flash memory cells with a conditioning signal to adjust and equalize their threshold voltage distributions prior to an erase operation;
A related object of the present invention is to provide a circuit and method for generating such conditioning signal, so that threshold voltage distributions can be finely controlled by a series of conditioning signals having predetermined magnitudes, durations, and similar signal characteristics;
Another object of the present invention is to provide that such conditioning signals can be custom tailored based on the particular processing implementation for such memory cell array, or, alternati

Affiliated with

Also associated with

Rating

Method for manufacturing non-volatile memory cell array does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for manufacturing non-volatile memory cell array, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing non-volatile memory cell array will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2937841