Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2000-01-19
2002-08-13
Jackson, Stephen W. (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C361S111000, C361S118000, C361S119000
Reexamination Certificate
active
06433979
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an electrostatic discharge (ESD) protection circuit for protecting an integrated circuit from damaging by electrostatic discharge, and more especially, to an ESD protection circuit using semiconductor controlled rectifier (SCR) for mixed voltage application.
BACKGROUND OF THE INVENTION
Electrostatic discharge (ESD) phenomena, which normally occur on integrated circuits (ICs) when touched by charged human body or machines, have a grown importance in electric and semiconductor industry. Due to the extreme high-energy electrical pulse caused, the electrostatic discharges could damage the integrated circuit badly. As the semiconductor technologies tend to reducing device dimension and increasing circuit integration, the potentially destructive nature of ESD became more and more apparent. To prevent the ICs form failure by unexpected damage, the ESD phenomena should be suppressed, and protection circuits are often employed against ESD in addition to antistatic coatings to protect the primary circuit elements on IC chips.
In general, the ESD protection circuits for an IC chip are coupling to the contact ports, which typically refer to as pins or inputs/output pads, of the chip needed for protection. An ESD protection circuit is a bypass of the primary circuit and constructed with a trigger voltage at which a key junction enters avalanche breakdown and the bypass of protection circuit shorts to allow a great amount of current passing through and shunted to electrical ground. After the ESD protection circuit is triggered, a low impedance mode called snap-back occurs so that the bypassed current can flow through the protection circuit under a holding voltage that is much lower than the trigger voltage. The primary circuit is thus prevented from experience of ESD current.
An important conventional ESD protection circuit is semiconductor-controlled rectifier (also refer to as silicon controlled rectifier, SCR).
FIG. 1
shows a typical lateral SCR (LSCR) protection circuit in cross-sectional view of a wafer. The conventional LSCR is typically constructed in a P-type doped substrate
10
with an N-type doped well region
20
formed therein. A heavily doped P-type region
30
is formed in the N-type well region
20
to serve as the anode of the LSCR, and a heavily doped N-type region
40
is formed in the P-type substrate
10
outside the N-type well region
20
to serve as the cathode. Contact regions of the P-type substrate
10
and N-type well region
20
can be optionally formed as the P-type and N-type heavily doped regions
50
and
60
respectively. In this structure, N-type region
20
is interposed between P-type regions
10
and
30
while the P-type region
10
is interposed between N-type regions
20
and
40
.
This LSCR device acts as a switch when a bias is provided with the anode potential positive with respect to the cathode potential. As the provided bias is at the normal operating level of the primary circuit, only leakage current flows through the LSCR device because the junction
15
between the N-well
20
and P-type substrate
10
is reverse biased. The LSCR is now considered to be “off”. As the added bias is raised positively beyond a certain level, which refers to as trigger voltage mentioned above, the junction
15
enters avalanche breakdown and a large number of electron-hole pairs are generated. This results in constructive feedback and allows a great current passes through the junction as well as the LSCR, at a holding level much lower than the trigger voltage. The LSCR switch is now “on” to bypass the ESD current and prevent the components of the primary circuit from damage.
Above conventional LSCR devices used for ESD protection encounter a problem about their high trigger voltage, which is typically around tens of volts, because they must be triggered beyond the breakdown voltage of junction
15
. A variety of circuit structures, which are desired for protection from ESD effect, may be damaged at the level below the trigger voltage of these LSCRs. A low voltage triggering SCR (LVTSCR) structure is thus developed to reduce the trigger voltage and thus increase the protection range.
FIG. 2
displays a cross-sectional view of a typical LVTSCR structure used for ESD protection. The typical LVTSCR substantially keeps all the LSCR's elements and retains their related configuration as illustrated in FIG.
1
. Three additional elements appear. A heavily doped N-type region
70
is formed at the boundary of P-type substrate
10
and N-type well region
20
. Gate oxide film
80
and gate electrode
90
are stacked on the substrate
10
between the two N-type doped regions
40
and
70
to form an NMOS transistor
100
with the N-type doped regions
40
and
70
as the source and drain regions. As can be seen in
FIG. 2
, a LVTSCR is formed with a LSCR coupling to an NMOS transistor at a common region, that is, the N-type doped region
40
in FIG.
2
.
In the LVTSCR structure, the gate electrode
90
of the NMOS transistor
100
is electrically connected to N-type doped region
40
so that the transistor
100
is normally not conducting. As the bias of the anode with respect to cathode rises, the NMOS transistor
100
enters breakdown prior to junction
15
, and thus the LVTSCR is triggered by the NMOS breakdown current at approximately the breakdown voltage of the NMOS transistor
100
instead of the breakdown voltage of junction
15
. For that the former breakdown voltage is typically much lower than the latter one as a result of the modern semiconductor fabrication technology, the trigger voltage of the LVTSCR is thus significantly reduced.
However, there are still some issues, such as the mixed voltage application, that must be considered when the LVTSCR devices are applied to ESD protection circuit. As known in the art, integrated circuits, as well as computer systems were designed historically to operate under five-volt power supply. As the electric and semiconductor fabrication technology progresses, and the application market develops, lower power consumption and higher device performance are required. Lower voltage standards were then introduced. A 3.3-volt system is employed.
The new lower voltage standard were not immediately fully adopted for all applications. Devices having new standard power supply are frequently used together with those having old standard power supply. Sometimes it is needed to make new, low-voltage devices interconnected to old, high-voltage devices. For such a mixed voltage system, it must be ensured that the circuit designed to operate at lower voltage standard would not be harmed when used in the high voltage application. However, in this case, the conventional LVTSCR manufactured for protecting the low-voltage device would face a high standard voltage across the thin gate oxide of the NMOS transistor thereof. Since the LVTSCR is employed for the low-voltage protection and generally fabricated simultaneously as the protected circuit formed, the gate oxide is not designed for withstanding the high standard voltage. The high standard voltage across the gate oxide would generate strong field, increase hot carriers, and result in degradation of oxide reliability and shortening of oxide lifetime (before oxide breakdown). Therefore, an effective ESD protection device fit for mixed voltage application is sought.
SUMMARY OF THE INVENTION
The present invention proposes a novel electrostatic discharge (ESD) protection circuit used for mixed voltage application. This ESD protection circuit utilized semiconductor-controlled rectifier (SCR) as the basic protection device for ESD current bypass. A lateral semiconductor-controlled rectifier (LSCR) or a floating well SCR can be chosen. In addition, N+ guard band in the N-well region or P+ guard band in P-type substrate can be optionally adopted for higher trigger current and increasing latch-up margin.
MOS transistors are employed to reduce the trigger voltage of the SCR. The MOS transistors are stacked in a cascode configurati
Baker & Botts L.L.P.
Jackson Stephen W.
Taiwan Semiconductor Manufacturing Co.
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