Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2000-03-09
2002-11-19
Sherry, Michael (Department: 2829)
Semiconductor device manufacturing: process
With measuring or testing
C438S016000, C438S800000
Reexamination Certificate
active
06482661
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to the manufacture of silicon wafers, and more particularly, to a method and system for manufacturing silicon wafers from ingots.
2. Brief Description of the Related Art
Referring to
FIGS. 1 and 2
, current manufacturing processes for silicon wafers
10
include cutting a flat
12
or a notch
13
at the periphery of the wafer to identify the crystalline orientation in the wafer. Practically all of the subsequent manufacturing processes utilize the flat or the notch to orient the wafer properly according to the wafer crystalline orientation.
One of the drawbacks of the current manufacturing process is that the notch removes a portion of the silicon wafer that could otherwise be utilized for the placement of integrated circuits. The notch also creates stress within the wafer making the wafer susceptible to stress cracks near or at the notch. The notch also is a particle generator, which makes it difficult to keep the wafer free from foreign particles during the wafer manufacturing process. A trend in silicon wafer manufacturing is for the manufacturers to make larger diameter silicon wafers. Currently, silicon wafers are manufactured with a 150 mm diameter. In the near future, it is expected that manufacturers will be making 300 mm diameter silicon wafers. As silicon wafer diameters continue to grow in size, the use of a notch will be counterproductive to the use of the larger size wafers. In addition; the stresses and the foreign particles associated with the notch will become more problematic during the manufacturing processes of larger diameter wafers.
Another drawback of the current manufacturing process used is that there is not a means to trace a wafer back to a particular ingot and, more particularly, there is not a means to trace a particular wafer to a particular location within a particular ingot.
Therefore, it would be desirable to have a manufacturing process that would provide traceability of a particular silicon wafer from a location within a particular ingot.
SUMMARY OF THE INVENTION
The present invention discloses a nondestructive method and system for manufacturing an ingot and a silicon wafer. The ingot's crystallographic orientation is identified and then marked by ingot indicia onto the ingot's outer surface. The ingot indicia may include the manufacturer's data as well as the ingot's specific information. The indicia also identifies the crystallographic orientation of the ingot. In the alternative, the indicia could simply be a single line identifying the crystallographic orientation of the ingot. A plurality of wafers are sliced from the ingot with a portion of the ingot indicia on each of the wafers. Wafer indicia is then marked onto a peripheral edge of the wafer. The wafer indicia includes a mark to identify the crystallographic orientation of the wafer as well as specific information about the ingot and the wafer. The wafer indicia may include dopant levels as well as resistivity and conductivity levels of the wafer.
According to one aspect of the method disclosed, a method for manufacturing a silicon wafer is disclosed. The method includes identifying the crystallographic orientation of the ingot and then marking indicia on the ingot and then slicing the ingot into wafers. The indicia on the ingot also may include information relating to the manufacturer of the ingot.
According to another aspect of the invention, a method for manufacturing a silicon wafer is disclosed, which includes marking indicia on a peripheral edge of the wafer. The indicia on the wafer includes a mark to identify the crystallographic orientation of the wafer. The indicia on the wafer also includes information relating to the manufacturer of the wafer.
According to another aspect of the invention, an ingot is disclosed that has a peripheral edge and indicia located on the peripheral edge. The indicia on the ingot includes a mark to identify the crystallographic orientation of the ingot. Further, the indicia on the ingot includes information relating to the manufacturer of the ingot.
According to yet another aspect of the invention, a silicon wafer is disclosed that has a peripheral edge and indicia located on the peripheral edge. The indicia on the wafer includes a mark to identify the crystallographic orientation of the wafer. Further, the indicia on the wafer includes information relating to the manufacturer of the wafer. The indicia on the wafer also includes information relating to the manufacturer of the ingot.
According to another aspect of the silicon wafer disclosed, the wafer has a peripheral edge that has a plurality of surfaces and wafer indicia is located on more than one peripheral edge surface.
In yet another alternative aspect of the silicon wafer disclosed, the wafer has a peripheral edge that has indicia located on the peripheral edge surface. The indicia includes information regarding integrated circuits that are located on the wafer.
REFERENCES:
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patent: 5716876 (1998-02-01), Muramatsu
patent: 5876819 (1999-03-01), Kimura et al.
patent: 5993292 (1999-11-01), Oishi et al.
patent: 6004405 (1999-12-01), Oishi et al.
patent: 6109529 (2000-08-01), Nelson, Jr.
patent: 6112738 (2000-09-01), Witte et al.
patent: 6182729 (2001-02-01), Banzawa et al.
Richards, Ernie, En Rada web site article entitled “If This Gold Ingot would But Speak!”, 1988, 1 page.*
Pierret, Robert F., Modular Series on Solid State Deivces—Semiconductor Fundamentals, vol. 1, Addison-Wesley, 1983, pp. 3-14.
Burns Doane , Swecker, Mathis LLP
Intergen, Inc.
Pert Evan
Sherry Michael
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