Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
2000-08-10
2002-04-09
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C438S627000, C438S629000, C438S633000, C438S692000, C438S693000
Reexamination Certificate
active
06368981
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and a Chemical Mechanical Polishing (CMP) apparatus employed therein, more particularly to a method and an apparatus using a damascene CMP process that prevents a so-called “dishing problem” in producing a buried wiring line.
2. Description of the Related Art
In LSI (Large Scale Integrated) circuits such as microprocessors, memories and a like, there is substantial incentive toward higher levels of integration density and design rules permitting smaller minimum feature sizes for individual circuit components or devices. In other words, as a semiconductor industry moves toward smaller and smaller device dimensions, a greater density of devices per silicon substrate is required. As the device dimensions shrink, width of wiring trenches or holes formed in insulation films also shrinks. Further, since wiring density has increased as described above, a so-called “multilevel metallization technology” has been developed, wherein a plurality of layers each of which is provided with a wiring line and a thickness are stacked together into a stack to form a semiconductor device.
In LSI circuits described above, such narrow dimensions of wiring lines lead to higher resistances, and therefore affect devices in their characteristics such as operation speeds and a like. Consequently, it is required to reduce resistance in the wiring lines. As conventional wiring materials for semiconductor devices such as LSI circuits and a like, there are aluminum (Al) or aluminum-based alloys, which are excellent in electric properties and workability. However, the aluminum-based alloys are poor in resistance to electro-migration and stress-migration. Under such circumstances, there are increasing tendencies to use copper (Cu) or copper-based alloys in place of the aluminum-based alloys since the copper-based alloys are excellent in resistance to electro-migration and stress-migration and smaller in electric resistance than the aluminum-based alloys.
On an other hand, as one of conventional structures adapted for use with a fine wiring line, there is a damascene wiring structure in which a trench for forming the wiring line (hereinafter referred to as a wiring line trench) is formed in an insulation film, and filled with metal to produce a buried wiring line.
FIG. 7
is a sectional view of a silicon substrate, illustrating a typical damascene structure. For example, as shown in
FIG. 11
in which the dishing
57
is exaggerated, an insulation film
52
which is constructed of a silicon oxide film is formed on a top surface of silicon substrate
51
. In the insulation film
52
, a wiring line trench
53
is previously formed. A copper film
55
is formed in the wiring line trench
53
through a barrier metal film
54
made of tantalum (Ta), so that a buried wiring line
56
constructed of these films
54
,
55
is formed. The buried wiring line
56
has its surface polished to a flat mirror finish by a well-known CMP process. In the buried wiring line
56
, the barrier metal film
54
serves as a diffusion barrier film to prevent electro-migration of copper from the copper film
55
to the insulation film
52
and further to the silicon substrate
51
through the insulation film
52
.
With reference to
FIGS. 8A
,
8
B and
8
C, a conventional method of manufacturing a semiconductor device will be now described step by step.
First, as shown in
FIG. 8A
, for example, the insulation film
52
, which is constructed of a silicon oxide film or a like, is formed over an entire surface of the silicon substrate
51
by a chemical vapor deposition (CVD) process or a like. Then, by using a well-known photolithographic process, the wiring line trench
53
is formed in the insulation film
52
to reach some midpoint in depth of the insulation film
52
. After that, as shown in
FIG. 8B
, by using a sputtering process or a like, the barrier metal film
54
(made of tantalum) and the copper film
55
are sequentially formed in this order over the entire surface of the silicon substrate
51
through the insulation film
52
provided with the wiring line trench
53
.
Then, the silicon substrate
51
is transferred to a CMP unit for performing the CMP process. Using this CMP unit, as shown in
FIG. 8C
, the copper film
55
formed on an uppermost surface of the barrier metal film
54
is removed by polishing. Then, as shown in
FIG. 11
, the copper film
55
and the barrier: metal film
54
both formed on the silicon substrate
51
is removed by polishing, so that the buried wiring line
56
is formed, whereby the semiconductor device is completed, wherein the dishing
57
is shown in exaggerated form for clarification.
FIG. 9
shows a cross-sectional view of the conventional CMP unit
60
used in the CMP process described above. As shown in
FIG. 9
, the conventional CMP unit
60
is provided with a polishing platen
61
to which a polishing pad
62
is attached. The polishing pad
62
is brought into contact with a surface of the silicon substrate
51
being polished. In operation, the polishing platen
61
is rotatably driven through its rotating shaft
63
in a condition in which a polishing or abrasive liquid is supplied from an abrasive liquid supply nozzle
64
onto the polishing pad
62
and retained thereon.
On an other hand, as is clear from
FIG. 9
, a pressure unit
65
for holding and forcing the silicon substrate
51
being polished is disposed above the polishing platen
61
. The pressure unit
65
is provided with a metal head
66
and a retainer
67
on which the metal head
66
is fixedly mounted. These components
66
,
67
of the pressure unit
65
define a space for receiving therein an air bag
68
. The air bag
68
serves as a flexible element, is brought into press-contact with a rear surface of the silicon substrate
51
, and functions to force the silicon substrate
51
against the polishing pad
62
which is rotatably driven when the pressure unit
65
is rotatably driven by its rotating shaft
69
.
In a polishing operation in which the conventional CMP unit
60
shown in
FIG. 9
is used: first, the silicon substrate
51
which is still in the step of
FIG. 8B
has its top surface brought into contact with the polishing pad
62
; and then, the abrasive liquid is supplied from the abrasive liquid supply nozzle
64
onto the polishing pad
62
in a condition in which both the polishing platen
61
and the pressure unit
65
are rotatably driven; whereby the copper film
55
of the silicon substrate
51
is polished, as shown in FIG.
8
C. In this case, since the air bag
68
which is large in elastic deformation is used to force a front surface of the silicon substrate
51
against the polishing pad
62
of the polishing platen
61
during the polishing operation, it is possible to polish a top surface of the copper film
55
to a flat mirror finish (shown in FIG.
8
C). In the conventional case, a same polishing operation is repeatedly performed to form the buried wiring line
56
of the semiconductor device (shown in
FIG. 11
in which the dishing
57
is exaggerated) until the barrier metal film
54
formed on an uppermost surface of the insulation film
52
of the silicon substrate
51
is completely removed.
As described above, when the barrier metal film
54
and the copper film
55
both formed on the top surface of the silicon substrate
51
through the insulation film
52
are removed by the CMP process to form the buried wiring line
56
in the conventional method of manufacturing the semiconductor device, the same pressure unit
65
is repeatedly used in individual process steps for polishing the copper film
55
and for polishing the barrier metal film
54
in a condition in which the air bag
68
continuously forces the front surface of the silicon substrate
51
against the polishing pad
62
of the polishing platen
61
.
As is clear from the above, in the conventional method of manufacturing the semiconductor device, since the same pressure unit
Sugai Kazumi
Tsuchiya Yasuaki
Anya Igwe U.
NEC Corporation
Smith Matthew
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