Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Ball or nail head type contact – lead – or bond
Reexamination Certificate
2000-12-14
2002-08-20
Everhart, Caridad (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Ball or nail head type contact, lead, or bond
C257S739000, C257S777000, C257S773000, C257S680000, C257S686000, C257S723000
Reexamination Certificate
active
06437451
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the manufacture and testing of semiconductor components. More particularly, this invention relates to an interconnect for electrically engaging semiconductor components having both bumped, and planar, terminal contacts.
BACKGROUND OF THE INVENTION
Semiconductor components, such as bare dice, chip scale packages, BGA devices and wafers can include bumped contacts. For example, bumped contacts, such as solder balls, allow a component to be surface mounted to a mating substrate (e.g., PCB) using a solder reflow process. This type of component is sometimes referred to as a “bumped” component (e.g., bumped die, bumped wafer). Semiconductor components can also include planar contacts. For example, components can include planar land pads, or planar bond pads.
For testing the integrated circuits contained on semiconductor components it is necessary to make temporary electrical connections with the bumped contacts, or with the planar contacts. Different types of interconnects have been developed for making these temporary electrical connections. For example, a wafer probe card is one type of interconnect that is used to test semiconductor wafers. Another type of interconnect, is contained within a carrier for temporarily packaging singulated components, such as bare dice and chip scale packages, for test and burn-in. The interconnects include contacts that make the electrical connections with the terminal contacts on the components.
Sometimes a semiconductor component can include both bumped contacts, and planar contacts. For example, a chip scale package can include solder balls bonded to land pads. Some of the land pads may not include a solder ball. For testing this type of component a two step process must be utilized. In a first test step, electrical connections are made to the bumped contacts using a first interconnect constructed for bumped contacts. In a second test step, electrical connections are made to the planar contacts using a second interconnect constructed for planar contacts.
It would be desirable for a single interconnect to be able to accommodate both bumped contacts and planar contacts. This would simplify the test procedure, and the equipment associated with test processes. Such an interconnect must be able to compensate for the different surface topographies of the bumped contacts and the planar contacts. In particular, the bumped contacts are raised above the surface of the component, while the planar contacts are substantially planar to the surface of the component. In addition, the bumped contacts can have different sizes and heights, such that the bumped contacts are not all located along a common plane. Similarly planar contacts can vary in size, location and planarity on the component.
Another problem with making temporary electrical connections with a component occurs when the contacts are located along a center line of the component. In particular, the component can tilt if the contact pressure is not applied directly along the center line of the component to the component contacts. It would be desirable for an interconnect to be configured to prevent tilting of the component during electrical engagement of the contacts.
The present invention is directed to an interconnect for making temporary electrical connections with semiconductor components having both bumped contacts and planar contacts. The interconnect includes first contacts constructed to center and retain the bumped contacts, and to accommodate variations in the size and planarity of the bumped contacts. In addition, the interconnect includes second contacts constructed to electrically engage the planar contacts.
SUMMARY OF THE INVENTION
In accordance with the present invention, an improved interconnect for testing semiconductor components having both bumped contacts and planar contacts is provided. Also provided are a test carrier, and a test system incorporating the interconnect.
The interconnect, simply stated, comprises: a substrate, a plurality of first contacts on the substrate for electrically engaging the bumped contacts, and a plurality of second contacts on the substrate for electrically engaging the planar contacts. Different embodiments are provided for the interconnect contacts including compliant embodiments, able to cushion contact forces, and to compensate for variations in the size and planarity of the contacts on the components. Preferably, either the first contacts or the second contacts on the interconnect are provided in a compliant embodiment.
In an illustrative embodiment, the first contacts comprise recesses in the substrate at least partially covered with a conductive layer. The recesses are configured to retain and electrically engage the bumped contacts. In an alternate embodiment, the recesses are formed in a polymer layer deposited on the substrate, which allows flexure in a z-direction. In another alternate embodiment the first contacts comprise conductive polymer donuts formed on a surface of the substrate. The polymer donuts are sized and shaped to compliantly retain, and electrically engage the bumped contacts.
The second contacts comprise projections on the substrate configured to simultaneously engage the planar contacts during electrical engagement of the bumped contacts by the first contacts. In addition, the second contacts have a height selected to space the component from the interconnect such that the bumped contacts are not excessively deformed during electrical engagement by the first contacts.
In an illustrative embodiment, the second contacts include penetrating projections for penetrating the planar contacts to a limited penetration depth. In an alternate embodiment, the second contacts comprise conductive polymer bumps. In another alternate embodiment, the second contacts have a planar tip portion configured to support and prevent tilting of the component, during electrical engagement of the bumped contacts by the first contacts.
Suitable materials for forming the substrate include silicon, ceramic, and plastic. With the substrate comprising silicon both the first contacts and the second contacts can be formed integrally with the substrate using an etching process. In the compliant embodiments a conductive polymer material, such as a metal filled silicone, or an anisotropic adhesive can be used to form the interconnect contacts. Using conductive polymers, the interconnect contacts are naturally resilient to provide compliancy for cushioning contact forces, and for accommodating variations in the size and planarity of the component contacts. In addition, the resiliency of the conductive polymer allows the interconnect contacts to be compression loaded during test procedures, while conductive dendritic particles within the conductive polymer, penetrate oxide layers covering the component contacts. The compliant contacts can be formed by stenciling, screen printing, or otherwise depositing, a viscous conductive elastomeric material in a desired pattern, followed by partial curing, planarization and then total curing.
The die level carrier is configured to retain singulated semiconductor components, such as bare dice and packages, in electrical communication with test circuitry. The die level carrier includes: a base, the interconnect mounted to the base, and a force applying mechanism for biasing the component against the interconnect.
The wafer level carrier is configured to retain a wafer, or portion of a wafer, containing multiple semiconductor dice. Alternately the wafer level carrier can be configured to retain, a wafer, or a panel containing multiple semiconductor packages.
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patent: 5341564 (199
Akram Salman
Farnworth Warren M.
Anya Igwe U.
Everhart Caridad
Gratton Stephen A.
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