Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1999-06-04
2002-08-20
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S311000, C438S287000
Reexamination Certificate
active
06436792
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of forming a device isolation structure in a semiconductor device employing an SOI (Silicon On Insulator) substrate.
2. Description of the Background Art
FIG. 44
is a cross-sectional view of a background art semiconductor device employing an SOI substrate. The SOI substrate which includes a silicon substrate
101
, a buried oxide film
102
and an SOI layer
103
has first and second device formation regions and a device isolation region. In each of the first and second device formation regions, a multilayer structure including a gate oxide film
104
and a gate electrode
105
formed on the gate oxide film
104
is selectively formed on an upper surface of the SOI layer
103
. In the device isolation region, an isolation oxide film
106
is formed on the upper surface of the SOI layer
103
.
The structure of the semiconductor device shown in
FIG. 44
is described in detail hereinafter using an instance where an N-channel MOS transistor is formed in each of the first and second device formation regions. A channel formation region
107
doped with a p-type impurity of a concentration of, for example, 1×10
17
to 1×10
18
/cm
3
is formed under each of the gate electrodes
105
in the SOI layer
103
. A well region
109
doped with a p-type impurity of a concentration of, for example, 1×10
17
to 5×10
18
/cm
3
is formed under the isolation oxide film
106
in the SOI layer
103
. A body region
110
doped with a p-type impurity of a concentration of, for example, 1×10
19
to 1×10
21
/cm
3
is selectively formed in the well region
109
. A source/drain region
108
doped with an n-type impurity of a concentration of, for example, 1×10
19
to 1×10
21
/cm
3
is formed between each of the channel formation regions
107
and the well region
109
in the SOI layer
103
.
An interlayer insulation film
111
is formed entirely on the SOI layer
103
. Contact holes
112
are selectively formed extending through the interlayer insulation film
111
from an upper surface of the interlayer insulation film
111
to the upper surface of the SOI layer
103
where the source/drain regions
108
are formed. A contact hole
114
is formed extending through the interlayer insulation film
111
and the isolation oxide film
106
from the upper surface of the interlayer insulation film
111
to the upper surface of the SOI layer
103
where the body region
110
is formed. The contact holes
112
and
114
are filled with a conductor.
A source/drain electrode
113
is formed on the upper surface of the interlayer insulation film
111
where each of the contact holes
112
is formed. The conductor which fills the contact holes
112
establishes electric connections between the source/drain electrodes
113
and the source/drain regions
108
. A substrate electrode
115
is formed on the upper surface of the interlayer insulation film
111
where the contact hole
114
is formed. The conductor which fills the contact hole
114
establishes an electric connection between the substrate electrode
115
and the body region
110
.
A method of forming the isolation oxide film
106
in the semiconductor device shown in
FIG. 44
is described hereinafter.
FIGS. 45 through 47
are cross-sectional views showing the background art method of forming the isolation oxide film
106
in order of process steps. Initially, a silicon oxide film
120
is formed by the CVD process and the like on the upper surface of the SOI layer
103
in which the channel formation regions
107
and the well region
109
are formed (FIG.
45
). Then, a photoresist
121
is formed on the silicon oxide film
120
in the device isolation region by the photolithographic technique (FIG.
46
). Using the photoresist
121
as a mask, anisotropic dry etching such as RIE (Reactive Ion Etching) which exhibits a higher etch rate in a direction of the depth of the SOI substrate is performed on the silicon oxide film
120
to expose the upper surface of the SOI layer
103
. An unetched part of the silicon oxide film
120
serves as the isolation oxide film
106
. Thereafter, the photoresist
121
is removed (FIG.
47
).
Such a background art method of forming the isolation oxide film is disadvantageous in that the dry etching is performed until the SOI layer
103
is exposed for the formation of the isolation oxide film
106
to form a damaged layer
123
containing defects
122
in the upper surface of the SOI layer
103
in the first and second device formation regions. Since heavy metals and the like are prone to accumulate in the damaged layer
123
and the SOI substrate includes the buried oxide film between the SOI layer and the silicon substrate, the SOI substrate is more difficult to recover from the damage to the SOI layer by heat treatment and the like than a CZ substrate and an FZ substrate. Thus, the gate oxide film
104
formed on the SOI layer
103
having the damaged layer
123
is decreased in reliability.
SUMMARY OF THE INVENTION
A first aspect of the present invention is intended for a method of forming a device isolation structure for providing electrical isolation between first and second semiconductor devices formed respectively in first and second device formation regions of an SOI substrate, the device isolation structure being formed on a device isolation region between the first and second device formation regions of the SOI substrate. According to the present invention, the method comprises the steps of: (a) forming at least a first insulation film and a first film in stacked relation in the order named on a main surface of the SOI substrate; (b) removing the first film in the first and second device formation regions; and (c) removing the first insulation film in the first and second device formation regions by wet etching.
Preferably, according to a second aspect of the present invention, in the method of the first aspect, the first film includes a second insulation film different in material from the first insulation film; and the first film is removed by anisotropic dry etching which exhibits a higher etch rate in a direction of the depth of the SOI substrate in the step (b).
Preferably, according to a third aspect of the present invention, in the method of the second aspect, the first insulation film is a silicon oxide film, and the second insulation film is a silicon nitride film.
Preferably, according to a fourth aspect of the present invention, in the method of the first aspect, the first film includes a conductive film, and the step (a) comprises the step of forming a second insulation film on the first film. The method further comprises the step of (d) forming a third insulation film at a side surface of the first film, the step (d) being performed after the step (c).
Preferably, according to a fifth aspect of the present invention, in the method of the fourth aspect, the conductive film is a polysilicon film doped with an impurity, and the step (d) comprises the steps of: (d-1) thermally oxidizing a surface of a resultant structure provided in the step (c); and (d-2) removing a thermal oxide film formed in the step (d-1) by the thermal oxidation of the main surface of the SOI substrate in the first and second device formation regions.
Preferably, according to a sixth aspect of the present invention, the method of the fifth aspect further comprises the step of (e) forming a sidewall including a fourth insulation film on respective side surfaces of the first insulation film, the first film and the second insulation film, the step (e) being performed after the step (d).
Preferably, according to a seventh aspect of the present invention, in the method of the sixth aspect, the step (e) comprises the steps of: (e-1) forming a fifth insulation film on a resultant structure provided in the step (d); (e-2) forming a sixth insulation film on the fifth insulation film; (e-3) performing anisotropic dry etch
Hirano Yuuichi
Maeda Shigenobu
Yamaguchi Yasuo
Mitsubishi Denki & Kabushiki Kaisha
Niebling John F.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Stevenson Andre′
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