Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal
Reexamination Certificate
2000-10-02
2002-10-08
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
C438S119000
Reexamination Certificate
active
06461883
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for manufacturing a LED array head to be used as recording light-emitting elements for forming a permanent visible image on a recording medium by means of an electrophotographic recording system and also to a LED array head prepared by using such a method.
2. Related Background Art
Self-scan type LED arrays (to be referred to as “SLEDs” hereinafter) are described in Japanese Patent Application Laid-Open Nos. 1-238962, 2-208067, 2-212170, 3-20457, 3-194978, 4-5872, 4-23367, 4-296579 and 5-84971, “Proposal of a Light Emitting Element Array to be used for an Optical Printer Integratedly Comprising a Drive Circuit” (Japan Hard Copy '91 (A-17)) and “Self-Scan Type Light Emitting Element (SLED) Using a PNPN Thyristor Structure” (The Institute of Electronics, Information and Communication Engineers (3. 5. '90)). Such self-scan LED arrays are attracting attention as light-emitting elements to be used for recording purposes.
FIG. 2
of the accompanying drawings is a circuit diagram of a known SLED.
FIG. 3
is a timing chart of control signals to be used for turning on all the elements. Now, the configuration and the method of driving the SLED will be described by referring to
FIGS. 2 and 3
.
Referring firstly to
FIG. 2
, VGA represents the ground voltage of the SLED and is connected to a plurality of diodes by way of respective resistors, which diodes are cascaded to start pulse &phgr;S. The SLED comprises transfer thyristors S
1
′ to S
5
′ arranged in array and light-emitting thyristors S
1
to S
5
also arranged in array and the gates of the thyristors of each column of the two rows are mutually connected. The gates of the two thyristors of the first column are connected to the signal input section for receiving start pulse &phgr;S, while the gates of the two thyristors of the second column are connected to the cathode of the diode whose anode is connected to the input terminal for receiving start pulse &phgr;S. This arrangement is repeated for the third and fourth columns and so on.
Now, the transfer aspect and the light emission aspect of the SLED will be described by referring to the timing chart of
FIG. 3. A
transfer operation of the SLED starts when the start pulse &phgr;S is shifted from 0V to 5V. When the start pulse &phgr;S is at 5V and the forward voltage fall of a diode is 1.4V, Va=5V, Vb=3.6V, Vc=2.2V and 0V from Vd onward, while the gate signals of the transfer thyristors S
1
′ and S
2
′ are respectively at 5V and 3.7V. When shift pulse &phgr;
1
is shifted from 5V to 0V under this condition, the transfer thyristor S
1
′ shows 5V at the anode, 0V at the cathode and 3.7V at the gate so that the transfer thyristor S
1
′ becomes ON because the requirements for turning ON the transfer thyristor S
1
′ are satisfied. However, if start pulse &phgr;S is shifted to 0V under this condition, Va
5V as the transfer thyristor S
1
′ is ON. This is because &phgr;S is being applied by way of a resistor and the anode and the gate show a substantially equal potential when the thyristor becomes ON. As a result, the requirements for keeping the first transfer thyristor S
1
′ ON are satisfied if start pulse &phgr;S becomes equal to 0V so that the first shift operation will be completed. If the light-emitting thyristor drive clock &phgr;I signal is shifted from 5V to 0V under this condition, the condition under which the transfer thyristor is turned ON is regained so that the light-emitting thyristor S
1
becomes ON to turn on the first LED. As the first LED is turned on, when the light-emitting thyristor drive clock &phgr;I is made to return to 5V, the anode and the cathode of the light-emitting thyristor S
1
no longer shows any potential difference so that the lowest holding current of the thyristor no longer flows and the light-emitting thyristor S
1
becomes OFF.
Now, the transfer of the ON condition from the transfer thyristor S
1
′ to the transfer thyristor S
2
′ will be discussed below. If the light-emitting thyristor S
1
becomes OFF, shift pulse &phgr;
1
remains to be 0V and hence the transfer thyristor S
1
′ is held ON so that the gate voltage of the transfer thyristor S
1
′ is Va
5V and that of the transfer thyristor S
2
′ is Vb=3.7V. When shift pulse &phgr;
2
is shifted from 5V to 0V under this condition, the transfer thyristor S
2
′ shows 5V at the anode, 0V at the cathode and 3.7V at the gate so that the transfer thyristor S
2
′ becomes ON. The transfer thyristor S
1
′ is turned OFF just as the light-emitting thyristor S
1
is turned OFF by shifting shift pulse &phgr;
1
from 0V to 5V after turning ON the transfer thyristor S
2
′. Thus, the ON condition is shifted from the transfer thyristor S
1
′ to the transfer thyristor S
2
′. Then, the light-emitting thyristor S
2
becomes ON as the potential of the light-emitting thyristor drive clock &phgr;I is shifted from 5V to 0V.
The reason why only the light-emitting thyristor that corresponds to the ON transfer thyristor is that the requirements for turning ON a thyristor are not met except the one adjacent to an ON thyristor because the gate voltage of a transfer thyristor that is not ON is equal to 0V. The adjacent thyristor also cannot be turned ON because the potential of the light-emitting thyristor drive clock &phgr;I becomes equal to 3.4V (by which the forward voltage of the light-emitting thyristor falls) as the light-emitting thyristor is turned ON and hence the gate and the cathode of the adjacent thyristor do not show any potential difference.
While the light-emitting thyristor becomes ON and emits light by making the potential of the light emitting thyristor drive clock equal to 0V in the above description, it is necessary to control the light emitting thyristor so as to make it actually emit light with that timing or not according to the applied data in an actual printing operation. In
FIG. 3
, image data and &phgr;D represents a control signal to be used for this purpose. The logical OR of &phgr;I and the image signal is externally determined for the &phgr;I terminal of the SLED and the potential of the &phgr;I terminal of the SLED is actually made equal to 0V to make the corresponding light emitting thyristor emit light only when the image data is at 0V, while the potential of the &phgr;I terminal of the SLED remains equal to 5V and the corresponding light emitting thyristor does not emit light when the image data is at 5V.
A LED array chip having a configuration as described above may comprise, for instance, 128 light emitting thyristors, which are sequentially controlled and selectively turned ON by means of the corresponding transfer thyristors.
FIG. 4
of the accompanying drawings is a schematic perspective view of a SLED array head, illustrating its configuration.
Referring to
FIG. 4
, the SLED array head comprises SLED semiconductor chips
211
, a base plate
212
which is made of a glass epoxy material or a ceramic material that may be used for printed-wiring boards and carries thereon the SLED semiconductor chips, a signal connector
219
for receiving external control signals and power supplied from an external power source, a power supply connector
220
for receiving power for feeding the array head, a supply circuit
222
, a supply cable
221
connecting driver substrate
217
and the supply circuit
222
, a lighting control circuit (driver IC)
218
for receiving external control signals and generating lighting control signals for the SLED semiconductor chips
211
, bonding wires for connecting output signals &phgr;
1
, &phgr;
2
, &phgr;S, &phgr;I and negative electrode side power input (GND in this example) to the SLED semiconductor chips, a driver substrate
217
carrying thereon the lighting control circuit (driver IC)
218
, the signal connector
219
and the power supply connector
220
and a flexible cable
216
connecting the driver substrate and t
Mine Ryuta
Sekiya Toshiyuki
Shiraishi Mitsuo
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