Registers – Records – Conductive
Reexamination Certificate
2000-09-20
2002-12-24
Lee, Michael G. (Department: 2876)
Registers
Records
Conductive
C235S451000, C235S487000, C235S380000
Reexamination Certificate
active
06497370
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to smart cards, and more particularly, to an input circuit for smart cards having an electrically erasable and programmable memory (EEPROM).
BACKGROUND OF THE INVENTION
Smart cards having an EEPROM, such as phone cards, are well known and commonly use a low-capacity memory of about 300 bits. A part of the memory contains, for example, codes identifying the card and/or its proprietor and/or its manufacturer. Another part of the memory may contain a unit counter, which is the case especially with phone cards.
The addressing of the memory, namely the read and/or write operations, is done sequentially. Three commands are usually enough to manage a memory of this kind. A shift and read command RE shifts the operation from one memory cell to the next memory cell so that the contents of the latter cell can be read. A write command WR is used to program the memory cell in which the operation is located. Finally, an initialization command RST is used to initialize the commands of the memory, namely to take position on the first cell of the memory pending an instruction.
Thus, to program the nth memory cell, the following commands are performed successively: an initialization command RST to take position on a first memory cell, (n−1) shift and read commands RE to take position on the nth memory cell, and finally a write command WR to program the nth cell. If several cells of the memory have to be programmed successively, then to limit the number of commands to be performed, the shift and read commands RE and the write command WR could be sequenced without necessarily and systematically carrying out a performance of an initialization command RST after each write command WR. However, the instructions have to be communicated with care by the reader. Indeed, the involuntary programming of certain cells of the memory may put the card out of operation and thus make it unusable. In the prior art, the shift and read command RE, the write command WR and the initialization command RST are encoded in the form of two binary data elements A and B and transmitted to the card in the form of two binary signals SA, SB. These binary signals SA, SB are transmitted by direct contact between output terminals of the reader and corresponding input terminals of the card. For example, the initialization command RST is encoded by A=0 and B=0, the shift and read command RE is encoded by A=0 and B=1 and the write command WR is encoded by A=1 and B=1, the combination A=1 and B=0 being unused.
An input circuit, internal to the card, receives the two binary signals SA, SB and gives the shift and read command RE and/or write command WR and/or initialization command RST to the memory.
FIG. 1
shows a conventional structure of an input circuit
100
of this kind comprising five input terminals
101
to
105
to which there are respectively applied the first binary signal SA, a clock signal CLK, the second binary signal SB, a power supply voltage Vcc and a power-on signal POR. To each input terminal of the circuit
100
, there corresponds an output terminal of a reader
150
. Brushes located on the output terminals of the reader
150
provide the contact with the input terminals of the card when it is inserted into the reader.
The input circuit has a first read circuit
110
, a second read circuit
120
, and a decoding circuit
130
. The supply voltage Vcc powers all the elements of the input circuit
100
. The first read circuit
110
has a comparator
115
and a flip-flop circuit
116
. The comparator
115
has an input terminal known as a positive (+) terminal connected to the input terminal
101
of the input circuit
100
and an input terminal known as a negative (−) terminal to which a first reference voltage V
1
is applied. The comparator
115
also has an output terminal connected to a D input terminal of the flip-flop circuit
116
whose clock input and initialization terminals are connected respectively to the input terminals
102
and
105
of the input circuit
100
.
The first read circuit
110
works as follows. The comparator
115
compares the voltage level of the signal SA applied to its positive input terminal (+) with the first reference voltage V
1
and gives the result of the comparison at the D input terminal of the flip-flop circuit
116
in the form of a binary data element A. During an active edge of the clock signal CLK, the flip-flop circuit
116
transmits the data element A to its Q output terminal. The binary data element A is for example equal to “1” if the voltage level of the binary signal SA is higher than the first reference voltage V
1
. If not, it is equal to “0”. Similarly, the second read circuit
120
has a comparator
125
with a positive input terminal (+) connected to the input terminal
103
and a negative input terminal (−) to which there is applied the first reference voltage V
1
. The comparator
125
also has an output terminal connected to a D input terminal of a flip-flop circuit
126
whose clock input and initialization terminals are connected respectively to the input terminals
102
and
105
of the input circuit
100
. The second read circuit
120
works similarly to the first read circuit
110
: it receives the binary signal SB and produces a binary data element B representing the level of the binary signal SB with respect to the first reference voltage V
1
. The binary data element B is for example equal to “1” if the level of the binary signal SB is higher than the reference voltage V
1
. If not, it is equal to “0”.
By design, the comparators
115
and
125
have a hysteresis threshold ranging from a voltage threshold VH of about 2 V to a voltage threshold VL of about 0.8 V. To obtain efficient operation of the comparators
115
,
125
, preferably a first reference V
1
ranging between the threshold voltages VL and VH will be chosen. It should be noted that the flip-flop circuits
116
,
126
are not indispensable to the working of the read circuits
110
,
120
. They simply synchronize the binary data elements A, B arriving at the decoding circuit
130
.
The decoding circuit
130
has two input terminals
131
,
132
respectively connected to Q output terminals of the flip-flop circuits
116
and
126
. At three output terminals
135
to
137
, the decoding circuit
130
produces the three signals, namely the shift and read control signal RE, the write signal WR and the initialization signal RST which are applied to the memory
140
. With an input circuit of this kind, an instruction given by the reader is thus interpreted by decoding the logic state of the binary signals SA, SB received at the input terminals
101
and
103
.
However, the card must be protected against involuntary programming of certain cells of the memory, or else the smart card will be destroyed. For example, when the card is not being used and its input terminals are left floating, the read circuits
110
,
120
should not be capable of giving the combination A=1 and B=1 which corresponds to the write command WR.
For this purpose, a protection device may be added to the input circuit which favors a particular combination when the input terminals of the card are left floating, for example A=0 and B is equal to any value, or else A=1 and B=0 which corresponds to the shift and read command. The state A=1 and B=1 corresponding to a write command is thus prevented when the card is unused and the risks of involuntary programming of the card are minimized.
The protection device may for example be a parallel resistor ra such as the one shown in
FIG. 1
, an input terminal of the resistor r
a
being connected to the input terminal
101
and its other terminal being connected to the ground. Thus, when the input terminal
101
is left floating, the first read circuit
110
gives the binary data element A=0. The protection device may also comprise a resistor r
b
as shown in dashes in
FIG. 1
, which compri
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Jorgenson Lisa K.
Lee Michael G.
Paik Steven S.
STMicroelectronics S.A.
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