Data processing: measuring – calibrating – or testing – Calibration or correction system – Circuit tuning
Reexamination Certificate
1999-12-10
2002-10-08
Hoff, Marc S. (Department: 2557)
Data processing: measuring, calibrating, or testing
Calibration or correction system
Circuit tuning
C702S105000
Reexamination Certificate
active
06463395
ABSTRACT:
BACKGROUND OF THE INVENTION
Automatic test equipment plays a critical role in the manufacturing process for semiconductor devices. The equipment, often referred to as a “tester”, simulates an operating environment for devices at the wafer and package levels. By verifying the operability of each semiconductor device under varying conditions, manufacturers can realize high yields and provide a correspondingly higher level of reliability to customers. Not surprisingly, this translates into higher revenues for the semiconductor manufacturer.
Testers employed by semiconductor manufacturers generally include a computer workstation that runs test software for controlling the test. The software controls signal parameters for test vectors or waveforms that drive the semiconductor device. A pattern generator typically produces the waveforms and routes the signals to electronic circuits commonly referred to as pin electronics.
The pin electronics generally reside on one or more channel cards that route signals between the tester and one or more pins of a device under test (“DUT”). The pin electronics perform several tester functions and generally serve as a signal interface between the pattern generator and the DUT. One of the more important functions is to drive waveforms along a transmission path, or signal channel, to the pins of the DUT. The signal channel utilizes conductive signal traces, or microstrip transmission lines, in driving the waveforms to the pins of the DUT.
Dramatic increases in the speed of microprocessors and memory devices require testers to operate at ever-increasing speeds. For example, modern computer RAM designs have operating speeds surpassing 800 MHz. These and many other modern semiconductor devices need to be tested for operation at high frequencies, and thus high frequency waveforms must be passed between the tester and the DUT with minimal distortion. In order to prevent distortion of high frequency waveforms, it is important for the transmission lines to have controlled characteristic impedances. One method of correcting for impedance mismatches along the transmission lines is described in pending U.S. patent application Ser. No. 09/309,134, filed on May 10, 1999, which is incorporated by reference in its entirety into the present specification.
Individual channels typically employ convenient alternate paths for calibration purposes. The alternate paths are switched-in by “fly-by” relays. Unfortunately, when in an open condition, such relays effectively form “stubs” hanging from the transmission lines, introducing a shunt capacitance which creates a mismatch in the impedance along the transmission line. One way of dealing with this problem is to trim the transmission lines leading to the relays to make the lines thinner and thus introduce a series inductance which compensates for the added shunt capacitance.
The approach of matching impedance by thinning the transmission lines has the disadvantage that the relays add a relatively large shunt capacitance which requires a relatively large compensating series inductance. These large shunt and series reactances cause the circuit to oscillate at a relatively low frequency, thus setting an upper limit on the frequency range over which the pin electronics can be used. Another disadvantage of thinning the transmission line is that it increases dielectric losses and ohmic conductor losses due to the “skin effect”.
Thus, there is a need to compensate for the shunt capacitance added by devices along a transmission line without introducing low frequency resonances and without introducing unnecessary losses.
SUMMARY OF THE INVENTION
An apparatus and method for shunt capacitance compensation for a signal channel according to the present invention compensates for the shunt capacitance of devices forming stubs hanging from a transmission line, without introducing low frequency resonant frequencies and without introducing unnecessary losses.
To realize these advantages, at least two lengths of controlled impedance transmission line are typically separated by a “gap” or other effective discontinuity. A first signal lead of a device has two branches electrically couples the lengths of transmission line across the gap. One branch is connected to one of the lengths of transmission line, and the other branch is connected to the other length of transmission line, thereby forming a series connection with the lengths of transmission line. The two branches are connected together within or adjacent the device to minimize the effective length of the electrical “stub” represented by the device. This significantly reduces the shunt capacitance presented by the device itself. In addition, the two branches have series inductances which combine to substantially cancel a relatively small capacitance introduced by the device, thus substantially maintaining the characteristic impedance of the transmission line.
Thus, an apparatus and method for shunt capacitance compensation in a signal channel to which an electrical device is connected includes: a signal channel for transmitting signals to a destination; a device having a first signal lead forming first and second branches connected together at a location adjacent an operative portion of the device so that the first signal lead is electrically connected to the operative portion of the device, the branches being electrically coupled in series within the signal channel; and wherein the branches together have a combined series inductance which substantially cancels the shunt capacitance introduced by the device. In one embodiment, the signal channel includes first and second lengths of transmission line separated by a gap, the first branch being connected to the first length of transmission line and the second branch being connected to the second length of transmission line to electrically couple the branches in series within the signal channel. The first and second branches may be connected together at a location within the device, which may be a reed relay in which a reed is the operative portion of the device. In cases where the relay initially has a first ground lead, a second ground lead and a second signal lead, the first branch of the first signal lead is formed by disconnecting the first ground leed from the second ground leed and reattaching it to the first signal lead at a location adjacent the operative portion of the relay.
REFERENCES:
patent: 4564818 (1986-01-01), Jones
patent: 4633197 (1986-12-01), Vanderspool, II
patent: 4706203 (1987-11-01), Ramsdale et al.
patent: 4924172 (1990-05-01), Holmgren
patent: 4980799 (1990-12-01), Tobita
patent: 4988902 (1991-01-01), Dingwall
patent: 5017807 (1991-05-01), Kriz et al.
patent: 5282072 (1994-01-01), Nazarathy et al.
patent: 5339369 (1994-08-01), Hopfer et al.
patent: 5471492 (1995-11-01), Pidgeon, Jr. et al.
patent: 5499392 (1996-03-01), Grunwell
“Reed Relay Technical & Applications Information”, Coto Technology, date unknown.
Product Description for “12-Bit Schottky Barrier Diode Bus Terminator”, California Micro Devices, Jul. 26, 1999.
Coto Technology Product Selector Chart, Jul. 26, 1999.
Coto Technology 9400-9800 Series/Surface Mount Reed Relay Product Information, Jul. 26, 1999.
Coto Technology 9400-9800 Series/Surface Mount Reed Relay Product Information Sheet, Jul. 26, 1999.
Suarez Felix
Teradyne Legal Dept.
Teradyne, Inc.
LandOfFree
Shunt capacitance compensation structure and method for a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Shunt capacitance compensation structure and method for a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Shunt capacitance compensation structure and method for a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2930523