Shift register circuit

Details Shift register circuit Shift register circuit

2001-06-29

2002-11-19

Wambach, Margaret R. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Using shift register

C377S027000, C345S098000, C345S100000

Reexamination Certificate

active

06483889

ABSTRACT:

This application claims the benefit of Korean Patent Application No. P2000-50907, filed on Aug. 30, 2000, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to driving circuitry for a liquid crystal display, and more particularly, to a shift register of a liquid crystal display driving circuit.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) displays pictures by varying light transmissivity in the liquid crystal with selective application of electric field to the liquid crystal panel. In a matrix type LCD, pixel cells are arranged at intersections between data lines and scanning lines (e.g., gate lines). The data lines receive picture data from a data driver while the scanning lines receive scanning pulses from a scanning driver. The scanning driver includes a plurality of shift registers that sequentially apply the scanning pulses to the scanning lines.
FIG. 1
is a block circuit diagram showing a configuration of a related art shift register. Referring to
FIG. 1
, the related art shift register includes n stages
2
1
to
2
n
in cascade configuration and connected to respective n row lines ROW
1
to ROWn via output lines
4
1
to
4
n
. A start pulse SP is input to the first stage
2
1
, and each of the second to n-th stages
2
2
to
2
n
receives an output signal from its respective previous stage. Each of stages
2
1
to
2
n
is coupled to a row line ROWi connected to a pixel train and is selected using two of four clock signals C
1
to C
4
.
FIG. 2
is a detailed circuit diagram showing the i-th stage and (i+1)-th stage of the related art shift register. Referring to
FIG. 2
, the i-th stage
2
i
includes second and fourth NMOS transistors T
2
and T
4
connected to a ground voltage VSS, a third NMOS transistor T
3
connected to a supply voltage VCC, fifth and sixth NMOS transistors T
5
and T
6
connected to the output line
4
i
, and a first NMOS transistor T
1
supplied with an output signal g
i−1
at the previous stage.
The output signal g
i−1
present at the previous stage is applied to gate terminals of the first and fourth NMOS transistors T
1
and T
4
. Drain terminals of the second NMOS transistor T
2
, the fourth NMOS transistor T
4
and the sixth NMOS transistor T
6
are connected to a ground voltage VSS. Gate terminals of the second and sixth NMOS transistors T
2
and T
6
are connected to a source terminal of the fourth NMOS transistor T
4
and a drain terminal of the third NMOS transistor T
3
. The first and third clock signals C
1
and C
3
are applied to the i-th stage
2
i
, as shown in FIG.
2
.
An operation process of the i-th stage
2
i
will be explained with reference to
FIG. 3
below. First, the third clock signal C
3
is applied to the gate terminal of the third NMOS transistor T
3
. If the third clock signal C
3
is applied, then the third NMOS transistor T
3
is turned on. When the third NMOS transistor T
3
is turned on, a supply voltage VCC is applied to a second node P
2
to turn on the second and sixth NMOS transistors T
2
and T
6
. At this time, a first node P
1
and the output line
4
i
are initialized at the ground voltage VSS.
Subsequently, the output signal g
i−1
at the previous stage is applied as a start pulse. If the output signal g
i−1
from the previous stage is applied, then the first and fourth NMOS transistors T
1
and T
4
are turned on. When the fourth NMOS transistors T
4
is turned on, a second node P
2
is connected to the ground voltage VSS to turn off the second and sixth NMOS transistors T
2
and T
6
. On the other hand, when the first NMOS transistor T
1
is turned on, the output signal g
i−1
from the previous stage is applied to the first node P
1
. At this time, the fifth NMOS transistor T
5
connected to the first node P
1
is turned on.
After turning on the fifth NMOS transistor T
5
, the first clock signal C
1
is applied to the source terminal of the fifth NMOS transistor T
5
. The first clock signal C
1
applied upon turn-on of the fifth NMOS transistor T
5
is applied to the output line
4
i
. In other words, the i-th output line
4
i
is selected. After the clock voltage signal C
1
is applied to the output line
4
i
, the first clock signal C
1
is inverted into a low logic and thus the output line
4
i
also is supplied with a logic low voltage (i.e., a ground voltage).
Typically, a gate line swing voltage of the related art LCD is approximately 20 to 25V. In order to fulfill this swing voltage, swing voltages of the clock signals C
1
to C
4
input to the shift register should be set to more than 20V.
When the shift register is configured with NMOS transistors as shown in
FIG. 2
, clock signals C
1
to C
4
of 0 to 20V should be inputted for an application of a swing voltage of 20V to the gate line. On the other hand, when the shift register is configured with PMOS transistors, clock signals C
1
to C
4
of −8 to −12V should be inputted for an application of a swing voltage of 20V to the gate line. In other words, in the related art shift register, clock signals C
1
to C
4
having a large swing width are inputted from an external circuit (not shown) to the stages
2
1
to
2
n
.
The external circuit for supplying the clock signals C
1
to C
4
is configured within a single integrated circuit (IC) chip. The single IC chip generates clock signals C
1
to C
4
having a large swing width and applies them to the stages
2
1
to
2
n
.
However, while the external circuit of the related art (configured within the single IC chip) easily creates pulse signals having a low voltage (e.g., 0 to 10V), it has difficulty creating a voltage signal more than this low voltage or voltage signals at negative values. In other words, it is difficult to maintain reliable device characteristics according to the related art single IC chip because the external circuit has difficulty creating high voltages (e.g., more than 10V) and negative voltages. Thus, a high voltage or a negative voltage created by means of a single IC chip can cause erroneous operation resulting in adversely affected device characteristics.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a shift register circuit that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
In one aspect of the present invention, a shift register provides a reduced swing width of a clock voltage.
Additional features and advantages of the invention will be set forth in the description that follows; and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages in accordance with the present invention, as embodied and broadly described, the shift register circuit according to the present invention includes a plurality of stages, each of the plurality of stages associated with a respective one of a plurality of scanning lines for generating a first driving signal in response to first and second clock signals, and a plurality of level shifters, each of the level shifters being connected between one of the plurality of stages and its associated scanning line for applying a second driving signal to the scanning line in response to the first driving signal, wherein the second driving signal has a larger swing width than the first driving signal.
In another aspect of the present invention, a shift register circuit of the present invention includes a plurality of stages, each of the plurality of stages associated with a respective one of a plurality of scanning lines for generating a first driving signal in response to first and second clock signals, and a plurality of level shifters, each of the level shifters being connected between one of the plurality of stages and its associated sc

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