Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Pulse multiplication or division
Reexamination Certificate
2000-06-30
2002-12-31
Lam, Tuan T. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Pulse multiplication or division
C377S048000
Reexamination Certificate
active
06501815
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for frequency dividers generally and, more particularly, to a method and/or architecture for a loadable divide-by-N device with a fixed duty cycle.
BACKGROUND OF THE INVENTION
Conventional clock signals for systems requiring clocking (i.e., computer systems, microprocessors, controllers, etc.) are implemented using an oscillator to generate a reference signal and dividers to generate numerous clock signals. Clock signals can be characterized by a duty cycle. A duty cycle measures what portion of a clock signal period the clock signal is in a first state (i.e., a logic HIGH, or 1). For example, when a clock signal is in a HIGH state for one-half of the clock period and a LOW state for one-half of the period, the clock signal has a fifty percent (50%) duty cycle.
The clock signal can also be described as having a first half-cycle and a second half-cycle. The clock signal is in a first state during the first half-cycle and a second state during the second half-cycle. A half-cycle can be shorter or longer than half of the clock period depending upon the duty cycle of the clock signal. For example, a 50% duty cycle clock signal has half-cycles that are both one-half of the clock period. However, a clock signal with a 25% duty cycle has a first half-cycle that is one-quarter of the clock period and a second half-cycle that is three-quarters of the clock period. A clock signal with a 75% duty cycle has a first half-cycle that is three-quarters of the clock period and a second half-cycle that is one-quarter of the clock period.
In conventional clock generators, loadable dividers are used to divide the reference signal to generate a lower frequency clock signal. However, conventional loadable dividers can have either a very low (i.e., significantly less than 50%) or very high (i.e., significantly greater than 50%) duty cycle. When a 50% duty cycle clock is required, a conventional loadable divider is followed by a toggle flip-flop. The toggle flip-flop performs a divide-by-2 operation to get a 50% duty cycle. A disadvantage of using the toggle flip-flop to get a 50% duty cycle is that the conventional frequency divider cannot provide a 50% duty cycle clock with a frequency that is an odd fraction ( or multiple, if the divider is part of a phase lock loop circuit) of the reference frequency.
A loadable divider that could divide by an odd integer and provide a 50% duty cycle would be desirable.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a circuit configured to generate an output signal having a first frequency in response to a clock signal having a second frequency. The output signal may be in a first state and a second state for an equal number of half-cycles of the clock signal.
The objects, features and advantages of the present invention include a method and/or architecture for a loadable divide-by-N device that may (i) enable flexibility in output frequencies and/or (ii) improve frequency resolution by opening up post-divide space.
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patent: WO96/17305 (1996-06-01), None
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Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
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