Scannable interface to nonscannable microprocessor

Details Scannable interface to nonscannable microprocessor Scannable interface to nonscannable microprocessor

1993-07-01

1995-06-27

Beausoliel, Jr., Robert W.

Excavating

371 221, H04B 1700

Patent

active

054286239

ABSTRACT:
A diagnostic system for diagnosing states of circuit elements is described, wherein scannable circuits can be scanned without disturbing the state of unscannable circuits or violating protocols of busses on which unscannable devices are attached. One unscannable device is a standardized microprocessor. A processor interface circuit is coupled between the microprocessor and scannable processor circuits, via a processor bus, to insulate the scannable processor circuits from the unscannable microprocessor. The processor interface circuit is also scannable, including memory elements which affect the bus, by preventing a scan when the bus is in use. A scan is prevented through the use of a maintenance request signal from a scan controller to the processor interface circuit, and one or more maintenance approval signals from the processor interface circuit to the scan controller.

REFERENCES:
patent: 4780874 (1988-10-01), Lenoski et al.
patent: 5132974 (1992-07-01), Rosales
patent: 5260649 (1993-11-01), Parker et al.
patent: 5301156 (1994-04-01), Talley

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