Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2001-04-03
2002-10-08
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S077000, C327S052000, C327S065000
Reexamination Certificate
active
06462587
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit having a comparator circuit including at least one differential amplifier, and more particularly to an integrated circuit having a comparator, which is adaptable for a 1-bit A/D convertor or a digitizing circuit for translating the output signals of sensors, entering keys, or the like, and delivering a control signal to a switch for controlling a load.
2. Discussion of the Related Art
Output signals received from sensors, entering keys, or the like, which are treated as digital signals, may be considered to be, in the strict sense, analog signals having gentle rise profiles. Before such output signals are supplied to post-processing by a microcomputer, for example, the output signals must be converted into normal digital signals (binary logic signals) with high precision by a 1-bit A/D converter or a quantizing circuit. It is a common practice to use a buffer circuit for the digitizing circuit or the quantizing circuit. The buffer circuit has a unique threshold value. Because of this, the timing of changes in the logic level of the digital signal is unconditionally determined and fixed by the threshold value of the buffer circuit. As a result, it is impossible to adjust the rise point and the fall point of the digital signal. To cope with this, it is desirable to use a comparator constructed using a differential amplifier circuit of high gain. In this respect, there has been demanded the development of a semiconductor integrated circuit containing a plurality of comparators of that type in order to digitize a plurality of signals.
A conventional comparator using a high-gain differential amplifier circuit is shown in FIG.
12
. As shown, the comparator is made up of a current mirror circuit M, a differential amplifier circuit S
1
with two current paths L
1
and L
2
, and an inverter INV. The output section of the current mirror circuit operates as a constant current source for the differential amplifier circuit.
A drain current i
0
of an enhancement type (E-type) MOS transistor
2
flows, as a reference current, from a voltage source V
DD
to the input section of the current mirror circuit M, through a load MOS transistor
1
of the depletion type (D-type). A drain current i
3
, which depends on the reference current i
0
, flows through an E-type MOS transistor
10
in the output section.
In the first current path L
1
of the differential amplifier circuit S
1
, a drain current i
1
flows from the voltage source V
DD
and passes through a D-type MOS transistor
11
, which serves as a load transistor, and an E-type MOS transistor
15
, which serves as an amplifying transistor. In the second current path L
2
, a drain current i
2
flows from the voltage source V
DD
and passes through a D-type MOS transistor
12
, which serves as a load transistor, and an E-type MOS transistor
16
, which serves as an amplifying transistor. The gates of the amplifying transistors
15
and
16
are respectively connected to input terminals in
1
and in
2
as the input terminals of the differential amplifier circuit S
1
. The current paths L
1
and L
2
are connected to the output section (as a constant current source) of the current mirror circuit M. Accordingly, the following equation holds:
i
3
=i
1
+i
2
(1)
When the voltage applied to the input terminal in
1
is equal to the voltage applied to the input terminal in
2
, the following equation holds:
i
1
=i
2
i
3
/2 (2)
Under this condition, the differential amplifier circuit S
1
is in a balanced state.
When the voltage (input voltage V
in
) applied to the input terminal in
2
is higher than the voltage (reference voltage V
ref
) applied to the input terminal in
1
the current i
2
flowing through the MOS transistor
16
is increased by an increment &Dgr;i, which depends on the difference between the input voltages. Correspondingly, the current i
1
flowing into the MOS transistor
15
is decreased by &Dgr;i, as seen from the equation (1). A voltage drop across the load transistor
12
increases and the source potential (potential at node
102
) consequently drops.
When the input voltage V
in
is lower than the reference voltage V
ref
, the voltage drop across the load transistor
12
decreases and the source potential (potential at node
102
) rises. Accordingly, the potential (at node
102
) of the load transistor
12
is the amplified voltage, which depends on the difference between the voltages applied to the input terminals in
1
and in
2
, with the balancing voltage being the voltage drop caused by the balancing current (i
3
/2).
The inverter INV is made up of a MOS transistor
4
, which serves as a switching element, and a MOS transistor
3
, which serves as a load transistor, wherein both the MOS transistor
3
and the MOS transistor
4
are connected in series. The gate of the MOS transistor
4
receives the output voltage (differential amplifier voltage) V
102
present at the node
102
. The inverter INV produces a digitized signal V
OUT
as a binary signal having a high or low logic level which depends on the amplitude of the input voltage V
in
relative to that of the reference voltage V
ref
. As recalled, the input voltage V
in
is applied to the input terminal in
2
and the reference voltage V
ref
to the input terminal in
1
.
FIG.
13
(
a
) is a graph showing variations of the input potentials (V
in
and the reference voltage V
ref
) of the differential amplifier circuit S
1
with respect time t wherein the reference voltage V
ref
at the input terminal in
1
is higher than the respective threshold voltages V
th15
and V
th16
of the amplifying transistors
15
and
16
. At point A, the reference voltage V
ref
is equal to the input voltage V
in
(V
ref
=V
in
). At point P, the input voltage V
in
is equal to the threshold voltages V
th15
and V
th16
. FIG.
13
(
b
) is a graph showing variations of the output voltages (voltage V
101
, at node
101
and voltage V
102
at node
102
) of the differential amplifier circuit S
1
with respect to units of time t corresponding to the units of time of FIG.
13
(
a
) wherein the input voltages of differential amplifier circuit S
1
are those shown in FIG.
13
(
a
). A line consisting of alternating long and two short dashes indicates the threshold voltage V
th4
of the MOS transistor
4
. Point B indicates a voltage balanced state (V
101
=V
102
), which corresponds to the voltage balanced state at point A. At point C, the voltage V
102
at the node
102
is equal to the threshold voltage V
th4
.
When the input voltage V
in
is lower than the threshold voltages V
th15
and V
th16
, the amplifying MOS transistor
16
is in an off state, and the amplifying MOS transistor
15
is in an on state. The node
102
is pulled up to the source potential V
DD
, and the voltage V
101
at the node
101
is in the lowest level V
LOW
. When the input voltage V
in
exceeds the threshold voltages V
th15
and V
th16
, the amplifying MOS transistor
16
is also turned on, a normal differentially amplified output signal is present at the nodes
101
and
102
. When the input voltage V
in
is lower than the threshold voltages V
th15
and V
th16
, the output signal of the differential amplifier circuit S
1
, in the strict sense, is not the output signal when the differential amplifier circuit operates as a linear differential amplifier. However, this is not problematic in the digitizing operation because under this condition, the amplifier circuit has output characteristics which depend upon the input voltage difference.
In the case where the input voltage V
in
is lower than the threshold voltages V
th15
and V
th16
, the circuit shown in
FIG. 12
exhibits the following problems. FIG.
14
(
a
) is a graph showing variations of the input potentials (V
in
and the reference voltage V
ref
) of the differential amplifier circuit S
1
with respect to time t wherein the reference voltage V
ref
at the input terminal in
1
is lower than the threshold vo
Finnegan Henderson Farabow Garrett & Dunner LLP
Fuji Electric & Co., Ltd.
Tran Toan
LandOfFree
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