Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2000-12-29
2002-11-19
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S191000, C365S203000, C365S207000, C365S189110, C365S230060
Reexamination Certificate
active
06483765
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to semiconductor memory. More specifically, the invention relates to a semiconductor memory device and bit line connecting method thereof.
2. General Background and Related Art
Portable electronic devices, like a notebook computer or portable game devices, which are operated by battery power are designed to conserve power as much as possible to extend operating time for a given set of batteries. Many devices have significant amounts of memory so it is important that semiconductor memory devices be operated with low power consumption. Such devices have been developed. For example, see U.S. Pat. No. 6,061,276, entitled “SEMICONDUCTOR MEMORY DEVICE AND A SEMICONDUCTOR INTEGRATED CIRCUIT”.
Generally, a semiconductor memory device has a plurality of memory cells arranged in an array. Adjacent memory cell arrays shares a bit line sense amplifier array which is generally constructed and arranged between the memory cell arrays. A switch array is constructed and arranged between the bit line sense amplifier array and memory cell array. A control signal for switching is applied to the switch array.
The bit line sense amplifier is connected to any memory cell array according to an activation state of an adjacent memory cell array in order to read/write or refresh data to the memory cell array, and is not connected to an adjacent another memory cell simultaneously. The control is dependent on the switching state of the switching array.
Precharge and Activation operations are repeated periodically in order to read/write or refresh data by accessing to a word line of the memory cell array, and a switching array is driven for performing the above operations and a state of the control signal. In other words, an applied voltage is changed for driving the switching array.
Specifically, at the beginning, a voltage of each gate of the switching array is maintained at the power voltage Vdd level and thereafter the voltage, applied to the gate of the switching array, transitions to a high voltage Vpp level in order to make sure a memory cell array in which an access is selected and an adjacent bit line sense amplifier connect, and the voltage, applied to the gate of the switching array, is lowered to a ground voltage level in order to make a connection state of a memory cell array in which an access is not selected and an adjacent bit line sense amplifier disconnect. Thereafter, the control signal is set at the power voltage Vdd level for a precharge operation.
The following example is different from the above-mentioned: in a precharge state, a control signal is set at a high voltage Vpp and in an activation state, the control signal is set to lower a ground voltage level in order to disconnect a connection state of the switching array which is positioned at a non-selected memory cell array.
The operations of the conventional art must be performed every refresh cycle including activation and precharge operations. Accordingly, the higher the number of on/off times of the switching array is, the greater the power consumption is. A self-refresh mode can be provided at a low power consumption. Power consumption for on/off operations of the switching array is very high.
The switching array is operated frequently. It has a high load and uses a voltage Vpp that is higher than an operational voltage Vdd, for switching, and current must be provided to a circuit for providing the high voltage Vpp. Accordingly, a large amount of current is consumed for performing the above operations.
SUMMARY
With this background in mind, the present inventions feature a semiconductor memory arranged wherein a control signal for connecting bit line sense amplifiers drives at a high voltage level Vpp and thereafter prevents lowering it to an operational voltage level Vdd or a ground voltage level, thereby reducing a power consumption in data read, write and refresh operations.
The present inventions feature reduced power consumption of a semiconductor memory device by restricting a voltage change state of a control signal applied for controlling connection states of bit line sense amplifiers and memory cells.
Power consumption is reduced by limiting the voltage changes of a control signal. The control signal is provided for switching a switching array which causes a plurality of memory cell arrays and bit line sense amplifiers corresponding to the memory cell arrays to be connected together.
Some of the claimed inventions define a semiconductor memory device including a plurality of memory cell arrays. Bit line sense amplifier arrays includes a bit line sense amplifier arranged between the memory cell arrays and shared. One or more switching arrays are arranged between the bit line sense amplifiers and the memory cell arrays corresponding to the bit line sense amplifiers, respectively, and for switching the connection states therebetween. Bit line selection control means control repeatedly an activation and a precharge of each memory cell array and provide control signals corresponding to the activation and precharge to the switching arrays.
A bit line selection control unit provides mode control signals, wherein a control signal applied to switching arrays is a high voltage level. The modes of operations include: 1) a first mode for maintaining the high voltage level during a precharge period and successively an activation period; 2) a second mode for lowering it to a ground voltage level during successively an activation period after maintaining a high voltage level during a precharge period; 3) a third mode for maintaining a power voltage level during a precharge period and raising it to a high voltage level during successively activation period when the control signal is a power voltage level at the present activation period; 4) a fourth mode for maintaining the power voltage level during a precharge period and thereafter lowering to the ground voltage level during a successive activation period; 5) a fifth mode for maintaining the power voltage level during the precharge period and the successive activation period; 6) a sixth mode for raising to the power voltage level at the precharge period when the control signal is the ground voltage level at the present activation period and thereafter to a high voltage level at a successive activation period; 7) a seventh mode for raising to the power voltage level at the precharge period and thereafter maintaining the power voltage level at a successive activation period; and 8) an eighth mode for raising to the power voltage level at the precharge period and thereafter lowering to the ground voltage level at a successive activation period.
REFERENCES:
patent: 5016224 (1991-05-01), Tanaka et al.
patent: 5377151 (1994-12-01), Komuro
patent: 5594704 (1997-01-01), Konishi et al.
patent: 5973975 (1999-10-01), Raad
patent: 2 314 651 (1998-01-01), None
Ho Hoai
Hyundai Electronics Industries Co,. Ltd.
Pillsbury & Winthrop LLP
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