Nonvolatile semiconductor memory device

Details Nonvolatile semiconductor memory device Nonvolatile semiconductor memory device

1993-05-27

1995-06-27

Yoo, Do Hyun

Static information storage and retrieval

Floating gate

Particular biasing

36518907, 365201, 365210, G11C 700

Patent

active

054285704

ABSTRACT:
Memory cells are arrange in the row and column directions in the form of a matrix. A transistor as a load is connected to column lines. A sense amplifier is connected to the transistor. In a read check operation, in which the data in the memory cells are erased, and the erased state of each memory cell is checked, all the row lines are set in a non-selected state by a row decoder, and all the column lines are selected by a column decoder. In this state. the sum of currents flowing in the memory cells is detected by the sense amplifier. When the current detected by the sense amplifier becomes a predetermined value, a data erase operation is ended.

REFERENCES:
patent: 5258958 (1993-11-01), Iwahashi et al.
patent: 5299162 (1994-03-01), Kim et al.
patent: 5305273 (1994-04-01), Jinbo
patent: 5321655 (1994-06-01), Iwahashi et al.

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