Fishing – trapping – and vermin destroying
Patent
1989-01-23
1990-10-02
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437 43, 437101, 437229, 357 237, H01L 21312
Patent
active
049607197
ABSTRACT:
A method for producing an amorphous silicon thin film transistor array substrate comprising successively coating a gate insulating layer, an amorphous silicon layer and a protective insulating layer on a glass substrate provided with a gate electrode and a gate wiring having a predetermined shape, in such a manner as to not cover the connecting terminal region of the gate wiring. A protective insulating layer is patterned into a predetermined shape. After passing through a predetermined production process to produce an amorphous silicon thin film transistor array, at least a gate wiring and a source wiring are provided. The step of paterning the protective insulating layer comprises covering the connecting terminals of the gate wiring and the exposed region of the glass substrate with a photoresist.
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Tanaka Sakae
Watanabe Yoshiaki
Chaudhuri Olik
Seikosha Co. Ltd.
Wilczewski M.
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