Electric lamp and discharge devices: systems – Plural power supplies – Plural cathode and/or anode load device
Reexamination Certificate
2001-04-10
2002-11-12
Wong, Don (Department: 2821)
Electric lamp and discharge devices: systems
Plural power supplies
Plural cathode and/or anode load device
C315S169100, C345S060000
Reexamination Certificate
active
06479943
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for driving a plasma display panel in a matrix display scheme.
2. Description of the Related Art
At present, as thin display devices, AC (alternate current discharge) type plasma display panels (hereinafter referred to as the “PDP”) are commercially available in the market.
The AC type PDP comprises a plurality of column electrodes and a plurality of pairs of row electrodes which are arranged orthogonal to the column electrodes and form respective scanning lines in pair. The respective row electrode pairs and column electrodes are covered with a dielectric material defining a discharge space, and are constructed to form a discharge cell corresponding to one pixel at the intersection of each row electrode pair and each column electrode. In this event, since the PDP utilizes a discharge phenomenon, the discharge cells only have two states, i.e., a “light emission” state and a “non-light emission” state. Thus, a subfield method is typically employed to realize gradation luminance representations in the PDP.
In the subfield method, one field display period is made up of N subfields each of which corresponds to each of N bits in pixel data corresponding to an input video signal. Each of these N subfields is allocated a number of times of light emission (a light emission period) corresponding to a weighting for each bit digit in the pixel data to drive each discharge cell to emit light.
FIG. 1
is a diagram generally illustrating the configuration of a plasma display device which employs the subfield method as mentioned to drive the PDP in gradation representation.
In
FIG. 1
, a driver
100
converts an input video signal to digital pixel data corresponding to each of pixels, and applies pixel data pulses corresponding to the pixel data to column electrodes D
1
-D
m
of a PDP
10
which is employed as a plasma display panel. The driver
100
further applies a variety of driving pulses as described below to row electrodes X
1
-X
n
and Y
1
-Y
n
. One display line of the PDP
10
is comprised of a pair of row electrodes X, Y which are formed to intersect the column electrodes D
1
-D
m
, respectively. These column electrodes and row electrodes are formed with a dielectric material, not shown, interposed therebetween, and one pixel cell is formed at an intersection of a column electrode with a row electrode pair.
FIG. 2
is a diagram illustrating an example of a light emission driving format with which the driver
100
drives the DPD in one field period.
In the light emission driving format illustrated in
FIG. 2
, one field display period is divided into four subfields SF
1
-SF
4
. Then, in each of the subfields, a simultaneous reset process Rc, a pixel data writing process Wc, a light emission sustaining process Ic, and an erasure process E are performed, respectively.
FIG. 3
illustrates application timings (within one subfield) at which the driver
100
applies the column electrodes and row electrode pairs of the PDP
10
with a variety of driving pulses for performing each of the processes.
First, in the simultaneous reset process Rc, the driver
100
simultaneously applies a reset pulse RP
X
of negative polarity and a reset pulse RP
Y
of positive polarity to the row electrodes X
1
-X
N
and Y
1
-Y
N
, respectively. In response to the applied reset pulses RP
X
and RP
Y
, all discharge cells in the PDP
10
are discharged or reset to uniformly form a wall charge of a predetermined amount within the respective discharge cells. In this way, all the discharge cells are once initialized to “light emitting cells.”
Next, in the pixel data writing process Wc, the driver
100
first converts an input video signal to 4-bit pixel data. The first bit of the pixel data is used in the pixel data writing process Wc in the subfield SF
1
; the second bit in SF
2
; the third bit in SF
3
; and the fourth bit in SF
4
, respectively, and the following processing is performed. For example, in the pixel data writing process Wc in the subfield SF
1
, a pixel data pulse at a high voltage is generated when the first bit of pixel data is at logical level “1”, and the pixel data pulse at a low voltage (zero volt) is generated when the first bit is at logical level “0.” Then, the driver
100
sequentially applies the column electrodes D
1
-D
m
as illustrated in
FIG. 3
with a group of pixel data pulses PD
1
, PD
2
, PD
3
, . . . , PD
n
, each of which is comprised of m pixel data pulses, each corresponding to the first to n-th display lines in the PDP
10
. Further, the driver
100
generates a scanning pulse SP of negative polarity as illustrated in FIG.
3
and sequentially applies the scanning pulse SP to the row electrodes Y
1
-Y
n
at the same timing at which the group of pixel data pulses DP are each applied. Here, a discharge occurs only in discharge cells at intersections of the “rows” applied with the scanning pulse SP with the “columns” applied with the pixel data pulses at the high voltage (selective erasure discharge), thereby selectively erasing the wall charges which have remained in the discharge cells. The selective erasure discharge as mentioned causes the discharge cells initialized to “light emission cells” in the simultaneous reset process Rc to transition to “non-light emitting cells.” On the other hand, the selective erasure discharge does not occur in discharge cells which has been applied with the pixel data pulse at the low voltage simultaneously with the scanning pulse SP, so that these cells maintain the state of “light emitting cells.”
Next, in the light emission sustain process Ic, the driver
100
alternately applies the row electrodes X
1
-X
n
and Y
1
-Y
n
with sustain pulses IP
X
and IP
Y
as illustrated in FIG.
3
. Here, the number of times (period) the sustain pulses IP
X
and IP
Y
are applied in each light emission sustaining process Ic has been set corresponding to a weighting factor allocated to each subfield.
For example, as illustrated in
FIG. 2
, the driver
100
repeatedly applies the row electrodes X
1
-X
n
and Y
1
-Y
n
with the sustain pulses IP
X
and IP
Y
the following number of times (period) in continuation:
SF
1
:
1
SF
2
:
2
SF
3
:
4
SF
4
:
8
In this event, only discharge cells in which the wall charges remain after the end of the pixel data writing process Wc, i.e., the “light emitting cells” discharge to emit light each time they are applied with the sustain pulses IP
X
and IP
Y
to sustain the light emitting state the number of times (period) as mentioned above.
Next, in the erasure process E, the driver
100
applies the row electrodes X
1
-X
n
with an erasure pulse EP as illustrated in
FIG. 3
to simultaneously discharge all the discharge cells for erasure, thereby erasing the wall charges remaining in the respective discharge cells.
FIG. 4
is a table showing all possible patterns of light emission driving performed within one field period in a gradation driving mode which utilizes the subfield method.
For example, when a video signal corresponding to luminance “5” (corresponding to pixel data “0101”) is supplied, light is emitted in subfields SF
1
and SF
3
within SF
1
-SF
4
as illustrated in FIG.
4
. In this way, light is emitted once in SF
1
and four times in SF
3
, i.e., a total of five times, so that an intermediate luminance corresponding to the luminance “5” is viewed. In other words, an intermediate luminance display at 16 gradation levels is implemented in a luminance range from luminance “0” to luminance “15” as shown in
FIG. 4
by the gradation driving mode using the four subfields SF
1
-SF
4
, as described above.
In this event, as one field display period is divided into an increased number of subfields, a display image of higher quality is provided. Also, as the number of times the sustain pulses are applied is increased generally in each light emission sustain process Ic, a higher luminance display can be achieved.
However, since one field display period is regulated, it is not possible to thoughtlessly increase the numbe
Honda Hirofumi
Nagakubo Tetsuro
Shigeta Tetsuya
A Minh D
Pioneer Corporation
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