Semiconductor memory device with bank configuration

Details Semiconductor memory device with bank configuration Semiconductor memory device with bank configuration

2001-02-02

2002-04-16

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230080, C365S230060, C365S230010

Reexamination Certificate

active

06373774

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly, to addressing in a case where a memory and a logic circuit are integrally formed on one chip.
2. Description of the Background Art
In design of an embedded dynamic random access memory that is constructed of a memory and a logic circuit driving the memory on one chip, a designer keeps on hand memory macros ready to use in which the number of bits in an array and the number of banks can be varied, in order to response to many requirements.
Description will be given of a conventional embedded memory macro using
FIG. 21. A
memory macro shown in
FIG. 21
has a 4-bank configuration each bank of which has a memory capacity of 8 Mbits and realizes a total memory capacity of 32 Mbits. A bank B
0
is constructed of blocks B
0
a
and B
0
b
disposed on both sides of a central control band
900
. Likewise, banks B
1
, B
2
and B
3
are constructed of pairs of blocks, B
1
a
and B
1
b
; B
2
a
and B
2
b
; and B
3
a
and B
3
b
, respectively disposed both sides of the central control band
900
. Each bank includes a plurality of memory cells M disposed in a matrix arrangement; a plurality of word lines (WL) disposed in correspondence to a plurality of rows and a plurality of bit lines (BL) disposed in correspondence to a plurality of columns. It should be appreciated that, in an example shown in
FIG. 21
, each block has 512 word lines.
In the central control band
900
, a signal line
902
is disposed for transmission of an address. The signal line
902
transmits a signal output from an address buffer
904
. A row decoder
906
performs row selection according to an output of the signal line
902
.
The banks B
0
, B
1
, B
2
and B
3
are configured such that four 2-Mbit memory blocks are stacked. A memory capacity can be adjusted in memory blocks of 2 Mbits as a unit.
Further, the bank configuration is not limited to the 4-bank configuration but there can also be adopted a 2-bank configuration in which the entire memory blocks are grouped into two banks or a 1-bank configuration in which the entire memory blocks are used as one bank.
In each memory block, a redundant word line is disposed. Any defective word line can be replaced with a redundant word line not only in a memory block in which the redundant word line is disposed, but also in any of 4 memory blocks in the same bank in which the redundant word line is disposed.
In this configuration, a row address specifying a row direction, input externally, is latched at an address buffer
904
and sent to the signal line
902
disposed in the central control band
900
at a proper timing. At this time, part of the row address is predecoded. The row address
906
is sent from the signal line
902
running through the central control band
900
. A signal received from the signal line
902
is decoded by the row decoder
906
.
A word line WL is activated by the row decoder
906
. Furthermore, a memory cell M is selected according to a column address, input externally. When a read operation is specified by the logic circuit, a data on a selected memory cell is output to the logic circuit. When a write operation is specified by the logic circuit, a data received from the logic circuit side is written onto a selected memory cell.
Description will be given of an address map for a row address in a memory macro with such a configuration. In the figure, RA
0
to RA
12
indicates respective row address signals, and BA
0
to BA
1
indicates respective bank address signals. A mark “/” means inversion. For example, when /RA
12
is at H level if the row address signal RA
12
is at L level. Further, m
0
to m
15
indicates memory blocks.
Referring to
FIG. 22
, in a 1-bank configuration, the row address signals RA
9
to RA
12
are used in order to specify a memory block. The memory block m
0
is selected by activating the row address signals /RA
12
, /RA
11
, /RA
10
and /RA
9
; the memory block m
1
is selected by activating the row address signals /RA
12
, /RA
11
, /RA
10
and RA
9
; the memory block m
2
is selected by activating the row address signals /RA
12
, /RA
11
, RA
10
and /RA
9
; and the memory block m
3
is selected by activating the row address signals /RA
12
, /RA
11
, RA
10
and RA
9
.
The memory block m
4
is selected by activating the row address signals /RA
12
, RA
11
, /RA
10
and /RA
9
; the memory block m
5
is selected by activating the row address signals /RA
12
, RA
11
, /RA
10
and RA
9
; the memory block m
6
is selected by activating the row address signals /RA
12
, RA
11
, RA
10
and /RA
9
; and the memory block m
7
is selected by activating the row address signals /RA
12
, RA
11
, RA
10
and RA
9
.
The memory block m
8
is selected by activating the row address signals RA
12
, /RA
11
, /RA
10
and /RA
9
; the memory block m
9
is selected by activating the row address signals RA
12
, /RA
11
, /RA
10
and RA
9
; the memory block m
10
is selected by activating the row address signals RA
12
, /RA
11
, RA
10
and /RA
9
; and the memory block m
11
is selected by activating the row address signals RA
12
, /RA
11
, RA
10
and RA
9
.
The memory block m
12
is selected by activating the row address signals RA
12
, RA
11
, /RA
10
and /RA
9
; the memory block m
13
is selected by activating the row address signals RA
12
, RA
11
, /RA
10
and RA
9
; the memory block m
14
is selected by activating the row address signals RA
12
, RA
11
, RA
10
and /RA
9
; and the memory block m
15
is selected by activating the row address signals RA
12
, RA
11
, RA
10
and RA
9
.
Referring to
FIG. 23
, in a 2-bank configuration, a bank address signal BA
0
is assigned onto a signal line on which the row address signal RA
12
has been assigned in the 1-bank configuration, and the bank address signal BA
0
is used for switching-over between banks.
Referring to
FIG. 24
, in a 4-bank configuration, bank address signals BA
0
and BA
1
are assigned onto respective signal lines on which the row address signals RA
11
and RA
12
have been assigned in the 1-bank configuration, and the bank address signals BA
0
and BA
1
are used for switching-over between banks.
The row address signals RA
0
to RA
8
are used to specify word lines in a memory block regardless of a bank configuration.
In a case where a memory capacity of a memory macro in such a conventional memory chip is changed, a layout of a memory cell array is changed as shown in
FIGS. 25
to
27
.
FIG. 25
corresponds to a 1-bank configuration,
FIG. 26
corresponds to a 2-bank configuration; and
FIG. 27
corresponds to a 4-bank configuration. In any case of the bank configurations, a memory capacity is of 24 Mbits. Portions shaded by hatching in the figure indicate regions where no layout configuration is present in a 24-Mbit configuration.
Referring to
FIG. 25
, in a case of the 1-bank configuration, a portion other than addresses “1800” to “1FFF” in hexadecimal notation (the hexadecimal notation is hereinafter applied) of row addresses “0000” to “1FFF” are an address space.
Referring to
FIG. 26
, in a case of the 2-bank configuration, portions other than addresses “F00” to “FFF” of row addresses “000” to “FFF” are address spaces.
Referring to
FIG. 27
, in a case of the 4-bank configuration, portions other than addresses “600” to “7FF” of row addresses “000” to “7FF” are address spaces.
In such a manner, in a case where the 1-bank configuration is realized with a memory capacity of 24 Mbits, 8 Mbits in an edge portion of a memory cell array of 32 M bits are removed from the memory cell array of 32 Mbits. Further, in a case where the 2-bank configuration is realized with a memory capacity of 24 Mbits, a total of 8 Mbits in central and edge portions of a memory cell array is removed from the memory cell array of 32 Mbits. Still further, in a case where the 4-bank configuration is realized with a memory capacity of 24 Mbits, 2 Mbits in each of 4 regions of a memory cell array of 32 Mbits, obtained by dividing the memory cell array are removed from the memo

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