Integrated circuit structures with full dielectric isolation and

Details Integrated circuit structures with full dielectric isolation and Integrated circuit structures with full dielectric isolation and

1979-03-09

1981-04-07

Munson, Gene M.

357 4, 357 51, 357 59, H01L 2712, H01L 2702, H01L 2904

Patent

active

042610036

ABSTRACT:
Structure: An integrated circuit structure with full dielectric isolation comprising a supporting substrate having a planar surface of dielectric material and a semiconductor layer on said dielectric surface which forms a planar interface with the surface. Regions of oxidized silicon extend through the layer from said interface, surrounding and dielectrically isolating pockets of silicon in the layer; the oxidized silicon regions extend to the upper surface of the semiconductor layer where they are substantially co-planar with the silicon pockets. The devices of the integrated circuit are formed in said silicon pockets.
Method: The structure is fabricated by a novel method wherein a lightly doped silicon layer is deposited on a highly doped silicon substrate; surrounding oxidized silicon regions are then formed by selectively thermally oxidizing portions of the silicon layer to form oxide regions which are co-extensive with the oxidized areas and, thus, are co-planar with the remaining silicon pockets at both surfaces of the layer; a member having a dielectric surface interfacing with the silicon layer is formed, and the silicon substrate is removed by preferential electrochemical anodic etching to leave the silicon layer having the oxidized regions surrounding spaced silicon pockets mounted on said member.

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patent: 3385729 (1968-05-01), Larchian
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Appels et al. "Local Oxidation of Silicon and its Application . . . " Philips Res. Reports vol. 25 (4/70) pp. 118-132. _
Kamins "A New Dielectric Isolation Technique for Bipolar Integrated Circuits . . . " Proceeding IEEE (7/72) pp. 915-916.
Morandi "Planox Process Smooths Path to Greater MOS Density" Electronics (12/20/71) pp. 44-48.

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