Semiconductor device manufacturing: process – Making passive device
Reexamination Certificate
2001-01-23
2002-06-18
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making passive device
C438S622000
Reexamination Certificate
active
06406968
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of forming a memory device. More particularly, the present invention relates to a method of forming embedded dynamic random access memory (embedded DRAM).
2. Description of Related Art
Embedded dynamic random access memory (embedded DRAM) is a type of DRAM whose memory cell array and logic circuit array are integrated together in a silicon chip. Since accessing speed of embedded DRAM is very high, this type of memory is frequently deployed in high-speed data processing systems such as image processors. Each metal-oxide-semiconductor (MOS) transistor inside the logic circuit serves as a switch. Opening or closing of the switch is controlled by the application of a voltage to the gate terminal of the MOS transistor. For example, a conductive MOS transistor is considered in logic state ‘1’ and a cut-off MOS transistor is considered in logic state ‘0.’ By combining a plurality of these MOS transistors, an ideal logic circuit is formed.
Conventionally, DRAMs can be manufactured in two major routes. In one manufacturing route, MOS devices are formed in the memory cell region and the logic circuit region at the same time. Self-aligned bit line contacts, bit lines and self-aligned node contacts are formed in the memory cell region of the substrate while metallic layers and vias are formed in the logic circuit region dielectric layer. After forming a metallic layer over the vias in the logic circuit region, a dielectric layer is formed over the entire substrate. An opening that exposes the node contact is formed in the dielectric layer inside the memory cell region. The opening is used for fabricating a capacitor. A via opening that exposes a portion of the metallic layer is formed in the logic circuit region. Thereafter, steps necessary for forming a complete embedded DRAM are conducted.
In an alternative manufacturing route, manufacturing steps for forming the memory cell region are conducted first. Word lines and active regions are formed in the substrate and then bit line contacts and bit lines are formed over the substrate. After forming the node contact, a capacitor is formed over the substrate. When all necessary steps for fabricating the memory cell region are complete, gate structures and active regions are formed in the logic circuit region. This is followed by subsequent fabrication of the via and the metallic layer.
Both of the aforementioned routes of manufacturing DRAMs have some drawbacks, including.
1. In the first manufacturing method, both the memory cell region and logic circuit region are completed at the same time. However, the deposited dielectric layer after forming the node contact must have a considerable thickness so that a deeper opening can form in the dielectric layer. This is because deeper openings can produce a capacitor with a larger surface area and hence a greater capacitance. Nevertheless, a thick dielectric layer means that all via openings in the logic circuit region have very high aspect ratios. A high aspect ratio increases the difficulty of etching the dielectric layer to form vias that run all the way down into the metallic layer. This increases the difficulty of forming vias in the logic circuit region.
2. In the second manufacturing method, the memory cell region and the logic circuit region are fabricated separately. However, separate processing often produces a great step height between the memory cell region and the logic circuit region. The presence of a great step height frequently results in alignment problems in the logic circuit region during photolithographic and etching processes. In addition, the step height may affect subsequent device planarization processes as well.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method of forming the memory cell region and the logic circuit region of a dynamic random access memory (DRAM) such that vias are easier to form in the logic circuit region.
A second object of this invention is to provide a method of forming the memory cell region and logic circuit region of a dynamic random access memory such that a capacitor with a higher capacitance is ultimately produced.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming a dynamic random access memory. First, a substrate having a memory cell region and a logic circuit region is provided. The memory cell region and the logic circuit region each has a plurality of gate electrodes and a plurality of source/drain regions. A first dielectric layer is formed over the substrate. A liner pad is formed over the first dielectric layer in the memory cell region. A second dielectric layer is formed over the first dielectric layer. A bit line contact is formed in the second dielectric layer inside the memory cell region. The bit line contact and a portion of the liner pad are electrically connected. In the meantime, a contact is formed in the second dielectric layer and the first dielectric layer inside the logic circuit region. A bit line is formed over the second dielectric layer within the memory cell region. A first metallic layer is formed over the second dielectric layer within the logic circuit region. A third dielectric layer is formed over the second dielectric layer. A node contact that electrically connects with a portion of the liner pad is formed in the third dielectric layer and the second dielectric layer inside the memory cell region. At the same time, a first via that connects electrically with the first metallic layer is formed in the third dielectric layer inside the logic circuit region.
An intermediate dielectric layer is formed over the third dielectric layer. The intermediate dielectric layer within the logic circuit region has a plurality of intermediate metallic layers and a plurality of intermediate vias. The intermediate vias and the intermediate metallic layers are electrically connected together for adjusting height level of the intermediate dielectric layer and maintaining electrical connectivity within the logic circuit region. Openings are formed in the intermediate dielectric layer within the memory cell region such that each opening exposes a portion of the node contact. A capacitor is formed inside each opening within the memory cell region. A fourth dielectric layer is formed over the intermediate dielectric layer. A second via is formed in the fourth dielectric layer and the intermediate dielectric layer within the logic circuit region so that the second via and the intermediate metallic layer are electrically connected. A second metallic layer is formed over the fourth dielectric layer and then a fifth dielectric layer is formed over the fourth dielectric layer. A third via is formed in the fifth dielectric layer within the logic circuit region. Finally, a third metallic layer is formed over the fifth dielectric layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5981369 (1999-11-01), Yoshida et al.
patent: 6255151 (2001-07-01), Fukuda et al.
patent: 6281540 (2001-08-01), Aoki
Chien Sun-Chieh
Kuo Chien-Li
Nelms David
Nhu David
United Microelectronics Corp.
Wu Charles C.H.
Wu & Cheung, LLP
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