Static information storage and retrieval – Format or disposition of elements
Reexamination Certificate
2001-02-21
2002-06-18
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Format or disposition of elements
C365S053000
Reexamination Certificate
active
06407939
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains generally to integrated memory design, and in particular to dynamic random access memory design.
BACKGROUND OF THE INVENTION
Dynamic Random Access Memory (DRAM) devices are the most widely used type of memory device. The amount of single-bit addressable memory locations within each DRAM is increasing as the need for greater memory part densities increases. This demand for greater memory densities has created a global market and has resulted in memory part standards in which many memory parts are regarded as fungible items. Thus, many memory parts operate according to well known and universally adopted specifications such that one manufacturer's memory part is plug-compatible with another manufacturer's memory part.
There is a need in the art to produce memory parts which can fit within the packaging requirements of previous generations of memory parts. This need for “plug-compatible upgrades” requires that memory density upgrades are easy to effect in existing computer systems and other systems which use memory, such as video systems. This requires that greater density memory parts be placed within the same size packages as previous generations of memory parts with the same signal and power pinout assignments.
There is a further need in the art to more efficiently manufacture CMOS dynamic random access semiconductor memory parts which utilize space-saving techniques to fit the most memory cells within a fixed die size using a single deposition layer of highly conductive interconnect. There is a need in the art to manufacture such memory parts in a shorter production time using fewer process steps to produce more competitively priced memory parts.
SUMMARY OF THE INVENTION
The present invention solves the above-mentioned needs in the art and other needs which will be understood by those skilled in the art upon reading and understanding the present specification. The present invention includes a memory having at least 16 megabits (2
24
bits) which is uniquely formed in which highly conductive interconnects (such as metal) are deposited in a single deposition step. The invention is described in reference to exemplary embodiments of 16 and 32 Megabit Dynamic Random Access Memory in which only a single deposition layer of highly conductive interconnects are deposited in a single deposition step. The resulting semiconductor die or chip fits within existing industry-standard packages with little or no speed loss over previous double metal deposition layered DRAM physical architectures. This is accomplished using a die orientation that allows for a fast single metal speed path. The use of a single deposition layer metal design results in lower production costs, and shorter production time for a wide variety of memory parts, including but not limited to, DRAM, SDRAM, SRAM, VRAM, SAM, and the like. In addition, the architecture can be easily replicated to provide larger size memory devices.
According to one aspect of the present invention, a method of reducing parasitic resistance in an n-sense amplifier is described in which a ground bus is connected through row decoder logic to the n-sense amplifier.
REFERENCES:
patent: 3740732 (1973-06-01), Frandon
patent: 4314894 (1982-02-01), Schmelzer et al.
patent: 4862245 (1989-08-01), Pashby et al.
patent: 4910866 (1990-03-01), Allen
patent: 4949161 (1990-08-01), Allen et al.
patent: 4957878 (1990-09-01), Lowrey et al.
patent: 4958088 (1990-09-01), Farah-Bakhsh et al.
patent: 4975753 (1990-12-01), Ema
patent: 4989068 (1991-01-01), Yasuhara et al.
patent: 5021864 (1991-06-01), Kelly et al.
patent: 5042011 (1991-08-01), Casper et al.
patent: 5066999 (1991-11-01), Casper
patent: 5084406 (1992-01-01), Rhodes et al.
patent: 5131018 (1992-07-01), McAdams et al.
patent: 5150186 (1992-09-01), Pinney et al.
patent: 5155704 (1992-10-01), Walther et al.
patent: 5159206 (1992-10-01), Tsay et al.
patent: 5162248 (1992-11-01), Dennison et al.
patent: 5220221 (1993-06-01), Casper
patent: 5270241 (1993-12-01), Dennison et al.
patent: 5274276 (1993-12-01), Casper et al.
patent: 5278460 (1994-01-01), Casper
patent: 5292677 (1994-03-01), Dennison
patent: 5293342 (1994-03-01), Casper et al.
patent: 5295100 (1994-03-01), Starkweather et al.
patent: 5297086 (1994-03-01), Nasu et al.
patent: 5303180 (1994-04-01), McAdams
patent: 5309446 (1994-05-01), Cline et al.
patent: 5311481 (1994-05-01), Casper et al
patent: 5335203 (1994-08-01), Ishii et al.
patent: 5338700 (1994-08-01), Dennison et al.
patent: 5340763 (1994-08-01), Dennison
patent: 5340765 (1994-08-01), Dennison et al.
patent: 5347179 (1994-09-01), Casper et al.
patent: 5351213 (1994-09-01), Nakashima
patent: 5352945 (1994-10-01), Casper et al.
patent: 5357172 (1994-10-01), Lee et al.
patent: 5361002 (1994-11-01), Casper
patent: 5362002 (1994-11-01), Casper
patent: 5362666 (1994-11-01), Dennison
patent: 5367213 (1994-11-01), Casper
patent: 5369317 (1994-11-01), Casper et al.
patent: 5373470 (1994-12-01), Jones et al.
patent: 5394172 (1995-02-01), McLaury
patent: 5416347 (1995-05-01), Katto et al.
patent: 5445707 (1995-08-01), Toyama et al.
patent: 5446410 (1995-08-01), Nakukura
patent: 5473198 (1995-12-01), Hagiya et al.
patent: 5527663 (1996-06-01), Togawa et al.
patent: 5579256 (1996-11-01), Kajigaya et al.
patent: 5587607 (1996-12-01), Yasuda et al.
patent: 5625221 (1997-04-01), Kim et al.
patent: 5748552 (1998-05-01), Fung et al.
patent: 5815456 (1998-09-01), Rao
patent: 5835932 (1998-11-01), Rao
patent: 5838627 (1998-11-01), Tomishima et al.
patent: 5907166 (1999-05-01), Casper et al.
patent: 6274928 (2001-08-01), Casper et al.
patent: 3447722 (1985-07-01), None
patent: 0317161 (1989-05-01), None
patent: 0364186 (1990-04-01), None
patent: 0461313 (1991-12-01), None
patent: 0487468 (1992-05-01), None
patent: 1129444 (1989-05-01), None
patent: 4258161 (1992-09-01), None
patent: 5226614 (1993-09-01), None
patent: 06-085185 (1994-03-01), None
patent: 6350052 (1994-12-01), None
patent: 62-114121 (1997-05-01), None
Semiconductor World,(Document in Japanese) , pp. 96-99, (Aug. 1993).
“Micron Technology, Inc. ”,Micron Technology, Inc., specifications for DRAM,1-14, 1-16, (1995).
Comerford, R., et al., “Memory catches up”,IEEE Spectrum, ,34-35, (Oct. 1992).
Farmwald, M., et al., “A fast path to one memory”,IEEE Spectrum,,50-51, (Oct. 1992).
Foss, R., et al., “Fast Interfaces for DRAMs”,IEEE Spectrum,,54-57, (Oct. 1992).
Gjessing, S., et al., “A RAM link for high speed”,IEEE Spectrum,52-53, (Oct. 1992).
Inoue, M., et al., “A 16Mb DRAM with An Open Bit-Line Architecture”,IEEE International Solid-State Circuits Conference,pp. 246-247, (1988).
Jones, F., “A new era of fast dynamic RAMS”,IEEE Spectrum,43-49, (Oct. 1992).
Ng, R., “Fast computer memories”,IEEE Spectrum,36-39, (Oct. 1992).
Pinkham, R., et al., “A 128k×8 70-MHz Multiport Video RAM with Auto Register Reload and 8×4 Block WRITE Feature”,IEEE J. Solid-State Circuits,23, 1133-1139, (Oct. 1988).
Pinkham, R., et al., “A 128K×8 70MHz Video Ram with Auto Register Reload”,IEEE International Solid-State Circuits Conf.,236-237, ( Feb. 19, 1988).
Rideout, V.L., “One-device cells for dynamic random-access memories: A Tutorial”,IEEE Transactions on Electron Devices,vol. ED-26, No. 6, 839-851, (Jun. 1979).
Salters, R.H., “Fast DRAMS for sharper TV”,IEEE Spectrum,40-42. (Oct. 1992).
Yamada, K., et al., “A CPU Chip -On-Board Module”,Proc.: IEEE 43rdElectronic Components&Technology Conf.,Orlando, FL, pp. 8-11, (Jun. 1-4, 1993).
Le Vu A.
Schwegman Lundberg Woessner & Kluth P.A.
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