Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Emitter dip prevention or utilization
Reexamination Certificate
1999-12-20
2002-07-16
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Emitter dip prevention or utilization
C438S253000, C257S030000
Reexamination Certificate
active
06420238
ABSTRACT:
TECHNICAL FIELD
This invention relates to a method of fabricating high-capacitance capacitive elements in a semiconductor substrate.
BACKGROUND OF THE INVENTION
The invention relates particularly but not exclusively to a method of fabricating high-capacitance capacitive elements between successive metallization layers in a multi-level interconnection structure, and the ensuing description will refer to that field of application for convenience of explanation.
Capacitive elements are extensively employed as passive components in integrated electronic circuits. A first known technique for making the plates of a capacitor integrated in a semiconductor substrate includes forming a ply structure which has one or more polysilicon layers isolated from one another by a dielectric layer.
In particular, the conventional capacitive elements have a first plate which is formed in a polysilicon layer provided on the substrate. A dielectric layer is formed over the first capacitor plate. This dielectric layer is subsequently covered with a metallization layer from which the second plate of the capacitive element is made. Alternatively, the capacitive element may be formed from two superposed layers of polysilicon which are isolated from each other by a dielectric layer.
These prior solutions have deficiencies that interfere with the achievement of high quality features. For instance, using polycrystalline silicon (polysilicon) for the capacitor plates causes a high distributed surface resistance. This increased resistance becomes a major factor where capacitive elements of high capacitance, and hence large area, are provided for functional applications. In fact, the surface resistance of p+ doped polysilicon exceeds one hundred Ohms per square centimeter, while that of n+ polysilicon is more than a few tens Ohms per square centimeter.
Another important contributory factor is that capacitive elements having their plates formed from polysilicon layers are fabricated close to the substrate, so that the parasitic capacitance toward the substrate can be substantial, especially with capacitive elements of large area.
From this standpoint, forming the plates of such capacitive elements from layers belonging to metallization levels appears, therefore, to be a more effective solution.
A known technique for fabricating metal plate capacitors consists of forming, on a semiconductor substrate, a metallization layer which is later formed to provide the lower plates of the capacitive elements, as well as to provide interconnection pads.
Thereafter, a thin lower dielectric layer is deposited onto the entire exposed surface to form the dielectric layer between the capacitive element plates. The portions of this lower dielectric layer which lie above the metallization pads are then removed by a photolithographic process to allow a later connection to the next metallization layer. An upper dielectric layer is subsequently deposited onto the entire wafer surface. Openings are then provided in the dielectric layer at the locations of the metallization pads, and at the lower dielectric layer covering the lower capacitor plates.
It should be possible to etch away this upper dielectric layer in a fully selective manner with respect to the lower dielectric layer.
If the upper dielectric layer were unetchable with respect to the lower dielectric layer, then the formation of the contact openings may result in a damaged or destroyed lower dielectric layer, thus impairing the operability of the capacitive elements. Therefore, one factor in determining the quality of the capacitor is the etching of the upper dielectric layer while leaving the lower dielectric layer intact. If the lower dielectric layer is overetched or underetched, the quality of the capacitor is degraded.
The fabrication of the capacitive elements is completed by the deposition and photolithographic patterning of the next metallization level. The last-mentioned step defines the upper plates of the capacitive elements and the connection to the lower metallization layer through the openings.
SUMMARY OF THE INVENTION
Embodiments of the invention provide a method for fabricating high-capacitance capacitive elements that have structural and functional features whereby they can be integrated to the surface layers of the semiconductor circuits, thereby reducing their parasitic capacitances toward the substrate, while producing low-value surface resistances and obviating the critical aspects of the process steps for fabricating capacitive elements with which conventional methods are beset.
In embodiments of the present invention, a lower plate for a capacitive element is formed that is integrated in a semiconductor substrate from a metallization layer as employed for multi-level interconnection purposes, and forming an upper plate of the capacitive element from a sacrificial conductive layer.
Based on this principle, an embodiment of the invention is a method to fabricate the high-capacitance capacitive elements integrated in a semiconductor substrate by forming a dielectric layer over the semiconductor layer, depositing a metallization layer onto the dielectric layer, and then defining lower plates of the capacitive elements, as well as interconnection pads, by conforming said metallization layer. Next, an intermediate dielectric layer is formed onto the lower plates and interconnection pads, over the entire exposed surface of the semiconductor. Then a sacrificial conductive layer is deposited onto the intermediate dielectric layer, and upper plates of the capacitive elements are defined by conforming the sacrificial conductive layer.
The features and advantages of a method according to the invention can be more clearly understood by reading the following description of an embodiment thereof, given by way of example and not of limitation with reference to the accompanying drawings.
REFERENCES:
patent: 6180976 (2001-01-01), Roy
Ravesi Sebastiano
Santangelo Antonello
Iannucci Robert
Jorgenson Lisa K.
Lee Calvin
Seed IP Law Group PLLC
Smith Matthew
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