Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-05-07
2002-06-25
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S162000, C326S071000, C326S108000
Reexamination Certificate
active
06411140
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention generally relates to integrated circuits for use in computer systems and in particular to circuitry for use in inputting and decoding address signals within a synchronous integrated circuit having input buffers, decode units, sample and hold registers and the like.
2. Description of Related Art
State of the art integrated circuits for use in computer systems, such as cache-RAM integrated circuits and the like, require the fastest possible processing speeds and clock rates. Accordingly, it is desirable to gain speed improvements within all portions of the integrated circuit, particularly within input/output signal transmission paths. Within a cache-RAM integrated circuit, or similar synchronous integrated circuits, one component of the circuit which could benefit from speed improvement is the input path for address signals wherein input address signals are sampled and held in a clocked input register then decoded.
FIG. 1
illustrates a conventional address input path circuit
10
wherein address signals received along an input line
12
are stored in a register
14
then decoded by pre-decode and mid-decode units
16
and
18
, respectively. Additional decode units, not shown, may additionally be employed. Register
14
is clocked by a clock signal received along input clock line
20
by an input buffer
22
. Prior to triggering register
14
, the input clock signal is passed through a pulse generator
24
which generates a pulse of predetermined width on each rising edge of the input clock signal for use elsewhere within the integrated circuit containing address input path circuit
10
. Additionally, the clock signal is passed through a control logic unit
26
which, depending upon the implementation, may control the clock signal based upon control signals received elsewhere in the circuit.
For proper operation of register
14
, the clock signal must be received by the register during a time period during which the address signal received along line
12
is available to the register. In order to have margin for set-up time, the clock signal should be received by the register as late as possible. In order to have margin for hold time, the clock signal should be received by the register as early as possible. In order to respect both set-up and hold times, the clock signal is required to be received by the register within a given time window relative to the reception of the address signal at the input of the register. Preferably, the clock signal is received by the register at about a midway time during this time window, to provide substantially equal set-up and hold time margins for the address signal. However, passing the clock signal through pulse generator
24
and control logic
26
causes a certain amount of delay which may prevent the clock signal from reaching register
14
in a timely manner. Accordingly, a delay unit
28
is provided along the input path of the address signal prior to register
14
to delay the address signal by an amount sufficient to ensure that the address signal is available to the register during the time period in which the clock signal is received by the register.
Ideally, the set-up and hold time for register
14
is kept to a minimum thereby allowing the input address signal to be promptly passed on to the decode units for processing. In practice, however, it is often necessary to provide a fairly long set-up and hold time period to account for any timing differences or skew between availability of the address signals and receipt of the clock signal. If the set-up and hold time is too short, then any significant skew may cause the clock signal to be received either before or after the set-up and hold period, resulting in loss of the input address data.
One source of timing skew occurs as a result of process variations in the fabrication of input buffers
13
and
22
.
FIG. 2
illustrates an exemplary conventional input buffer cell
30
subject to process variations. Input buffers
13
and
22
of
FIG. 1
may be composed of a number of input buffer cells with one cell per individual input line. Buffer cell
30
includes a first inverter stage
32
and a second inverter stage
34
. Inverter stage
32
includes a PMOS device
36
and NMOS
38
. Although not shown, inverter stage
34
may incorporate a similar device arrangement. Collectively, the pair of inverters of the input buffer cell operate to receive, and perhaps modify, an input signal. The input buffer cell may, for example, modify the voltage range of the input signal to range from between 0 to 3 volts to between 0 to 5 volts. Although the input buffer cell of
FIG. 2
may adequately operate to achieve those results, the use of both PMOS and NMOS devices results in timing skews as a result of process variations between the PMOS and NMOS devices. As such, signals sent simultaneously through two different input buffer cells configured as in
FIG. 2
will likely be output by the input buffers with a slight timing difference or skew. This skew is especially noticeable when one input is rising and another input is falling. Hence, if implemented using the buffer cells of
FIG. 2
, the input buffers of
FIG. 1
will likely output their respective address or clock signals subject to a timing skew affecting the receipt of the signals by the register. To compensate for the possibility of such a timing skew, the overall set-up and hold time of the register must be set to a somewhat longer time period than would otherwise be desirable, resulting in overall poorer timing specifications for the entire integrated circuit containing the register.
FIG. 3
illustrates one possible solution for eliminating the process skew problems in the configuration of FIG.
2
. More specifically,
FIG. 3
illustrates an input buffer cell
40
having a pair of inverter stages
42
and
44
with individual device components of inverter stage
42
separately shown. (Inverter stage
44
may have a similar configuration to the first inverter stage of
FIG. 2.
) As can be seen, inverter stage
42
includes a pair of NMOS devices
46
and
48
with a gate of device
46
connected to a power supply and a gate of device
48
connected to the input. NMOS device
46
is smaller in size and strength than NMOS device
48
. With this configuration, timing skew problems resulting from process variations between PMOS and NMOS devices are avoided because only NMOS devices are employed. Thus, by configuring the input buffers of
FIG. 1
using the NMOS-only cell configuration of
FIG. 3
, timing skew as a result of process variations between the address signals and the clock signals is reduced thereby allowing a more precise set-up and hold time to be specified for the register. Unfortunately, although the NMOS configuration of
FIG. 3
helps eliminate process skew problems, significant power consumption occurs as a result of leakage current within the input buffer cell. More specifically, by employing two NMOS devices in series between a power source and ground, a DC path is provided, thereby consuming significant power. Accordingly, relatively large current flows through the first inverter stage
42
, particularly, when the input is held high. Additionally, some current passes through the second inverter stage
44
when the input is held low. The current drawn through the first inverter is caused by the two NMOS devices both being in an active state when the input is held high. The current flow through the second inverter
44
is caused by a voltage drop across NMOS pull-up device
46
when the input is held low. This voltage drop results in a voltage level at the input of the second inverter
44
which is not high enough to completely turn off the PMOS device (not separately shown) of the second inverter resulting in further leakage current.
Hence, the input buffer configuration of
FIG. 3
reduces timing skew as a result of process variations but does so at the expense of consuming significantly greater current.
FIG. 4
illustrates yet another configuration for
Cypress Semiconductor Corporation
Lam Tuan T.
Wagner , Murabito & Hao LLP
LandOfFree
Method and apparatus for reducing skew between input signals... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for reducing skew between input signals..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for reducing skew between input signals... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2915923