Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-01-26
2002-04-09
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S701000, C257S057000
Reexamination Certificate
active
06368976
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same. More particularly, the present invention relates to a semiconductor device having an insulation film with a sufficient film thickness difference between a control gate and a floating gate, and a method for manufacturing the same.
2. Related Art
FIGS. 6-12
show a semiconductor device (split gate flash memory) in cross section, manufactured by a conventional method.
As shown in
FIG. 6
, the surface of a P-type silicon substrate
1
is subjected to a dry-oxidation at 1000° C. to form a gate oxide film
2
on the P-type silicon substrate
1
. A polycrystal silicon film
3
is deposited on the gate oxide film
2
by a reduced pressure CVD (Chemical Vapor Deposition), and an anti-oxidation film
4
composed of Si
3
N
4
is deposited on the polycrystal silicon film
3
. Then, a resist
5
is coated on the anti-oxidation film
4
, and the resist
5
is exposed and developed to thereby form an opening
6
over an area where a floating gate is formed.
Referring to
FIG. 7
, the anti-oxidation film
4
that is exposed through the opening
6
is dry-etched using the resist film
5
as a mask, to thereby form an opening
7
in the antioxidation film
4
.
Referring to
FIG. 8
, the resist film
5
is removed. Then, the polycrystal silicon film
3
that is exposed through the opening
7
is selectively etched using the anti-oxidation film
4
as a mask to thereby form a selective oxide film
8
in the polycrystal silicon film
3
.
Then, referring to
FIG. 9
, the anti-oxidation film
4
is removed by heated phosphoric acid. Then the polycrystal silicon film
3
and the gate oxide film
2
are anisotropically etched in a vertical direction using the selective oxide film
8
as a mask, to thereby form a floating gate
9
under the selective oxide film
8
.
Then, referring to
FIG. 10
, a tunnel insulation film (SiO
2
film)
12
is formed on the entire surface including the floating gate
9
and the selective oxide film
8
by thermal oxidation or a high temperature reduced-pressure CVD method. Then, an insulation film
10
composed of Si
3
N
4
is deposited on the tunnel insulation film
12
.
Referring to
FIG. 11
, the insulation film
10
is anisotropically etched in a vertical direction to form a side insulation film
11
at a lower section of the side wall of the floating gate
9
. Then, the surface is washed with a cleansing solution of NH
4
OH+H
2
O
2
, for example, to remove a damaged layer (not shown) in the surface of the tunnel insulation film (SiO
2
film)
12
that is caused by the anisotropic etching.
Referring to
FIG. 12
, an N-type polycrystal silicon film
13
is deposited on the tunnel insulation film
12
within a phosphine (PH
3
) atmosphere by a reduced pressure CVD method. The polycrystal silicon film
13
and the tunneling insulation film
12
are patterned, such that the polycrystal silicon film
13
and the insulation film
12
remain in an area starting from a point on the selective oxide film
8
, across one side of the floating gate
9
, to a point on the P-type silicon substrate
1
. The remaining polycrystal silicon film defines a control gate
13
.
An N-type impurity such as arsenic, phosphorous and the like is introduced in the P-type silicon substrate
1
on both sides of the control gate
13
and the floating gate
9
to form diffusion regions
14
and
15
for source and drain regions in the P-type silicon substrate
1
.
In the split gate flash memory shown in
FIG. 12
, a high voltage (about 12 V) is applied to the control gate
13
to take out electrons from the floating gate
9
as indicated by an arrow
31
to perform an erase operation. On the other hand, electrons are injected from the substrate
1
as indicated by an arrow
33
to perform a writing operation.
It is noted that electrons flow only in a pass as indicated by the arrow
31
during the erase operation. Accordingly, while the tunnel insulation film (SiO
2
film) between the control gate
13
and the floating gate
9
in an area adjacent the arrow
31
has a predetermined dielectric strength, it needs to have a dielectric strength to withstand a voltage higher than an operating voltage in an area adjacent the arrow
32
. More specifically, the area adjacent the arrow
31
may have a dielectric strength to withstand a voltage of 7 V, and the area adjacent the arrow
32
needs to have a dielectric strength to withstand a voltage of about 16 V. Therefore, while the tunnel insulation film
12
has a relatively low dielectric strength in an upper portion of the side wall of the floating gate
9
, it needs to have a relatively high dielectric strength in a lower portion of the side wall of the floating gate
9
.
Under the circumstances, in the conventional split gate flash memory, a side insulation film
11
is formed on the lower portion of the side wall of the floating gate
9
to increase the thickness of the tunnel insulation film to thereby secure a sufficient dielectric strength in the area adjacent the arrow
32
between the control gate
13
and the floating gate
9
.
In the conventional semiconductor device described above, the side insulation film
11
is formed to change the thickness of the insulation film between the control gate
13
and the floating gate
9
. However, the formed side insulation film
11
does not provide a sufficient thickness difference in the insulation film between the portions adjacent the arrow
31
and the arrow
32
shown in FIG.
12
.
Also, when the Si
3
N
4
insulation film
10
is anisotropically etched in a vertical direction in the step of forming the side insulation film
11
shown in
FIG. 11
, a sufficient etching selection ratio with respect to SiO
2
of the tunnel insulation film
12
cannot be secured. As a result, the etching selection ratio often becomes low. As a consequence, SiO
2
films in the memory cell area and other areas may be etched more than designed, and thus the device characteristics may become unstable.
SUMMARY OF THE INVENTION
The present invention has been made in view of the problems described above. It is an object of the present invention to provide a semiconductor device having an insulation film between a control gate and a floating gate in which the insulation film has a sufficient thickness difference between at least two separated locations therein, and to provide a method for manufacturing the same.
In order to solve the problems described above, a semiconductor device in accordance with one embodiment of the present invention comprises a floating gate having a side wall with a generally vertical upper section and a tapered lower section, a second insulation film formed on the side wall by thermal oxidation, the second insulation film having a lower section thicker than an upper section thereof, a third insulation film formed on the second insulation film, and a control gate formed on the third insulation film.
A method for manufacturing a semiconductor device, in accordance with one embodiment of the present invention, comprises the steps of: anisotropically etching a polycrystal silicon film using a first insulation film as a mask to form an upper section of a floating gate under the first insulation film; etching the polycrystal silicon film using the first insulation film as a mask to form a lower section of the floating gate having a tapered side wall under the first insulation film; and forming a second insulation film by thermal oxidation on the side wall of the floating gate.
In the above-described method for manufacturing a semiconductor device in accordance with the present invention, the upper section of the floating gate is generally vertically etched. As a result, the insulation film is formed thinly on the upper vertical section even if a thermal oxidation process is conducted on the upper vertical section. On the other hand, the lower section of the floating gate is tapered, and therefore the lower section has a thick layer of polycrystal silicon that
Hogan & Hartson L.L.P.
Le Dung A
Nelms David
Seiko Epson Corporation
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