Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-11-20
2002-06-25
Shankar, Vijay (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C315S169100
Reexamination Certificate
active
06411269
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to the field of electronic displays, and, more particularly, field emission display (“FED”) devices.
As technology for producing small, portable electronic devices progresses, so does the need for electronic displays which are small, provide good resolution, and consume small amounts of power in order to provide extended battery operation. Past displays have been constructed based upon cathode ray tube (“CRT”) or liquid crystal display (“LCD”) technology. However, neither of these technologies is perfectly suited to the demands of current electronic devices.
CRT's have excellent display characteristics, such as, color, brightness, contrast and resolution. However, they are also large, bulky and consume power at rates which are incompatible with extended battery operation of current portable computers.
LCD displays consume relatively little power and are small in size. However, by comparison with CRT technology, they provide poor contrast, and only limited ranges of viewing angles are possible. Further, color versions of LCDs also tend to consume power at a rate which is incompatible with extended battery operation.
As a result of the above described deficiencies of CRT and LCT technology, efforts are underway to develop new types of electronic displays for the latest electronic devices. One technology currently being developed is known as “field emission display technology.” The basic construction of a field emission display, or (“FED”) is shown in FIG.
1
. As seen in the figure, a field emission display comprises a face plate
100
with a transparent conductor
102
formed thereon. Phosphor dots
112
are then formed on the transparent conductor
102
. The face plate
100
of the FED is separated from a baseplate
114
by a spacer
104
. The spacers serve to prevent the baseplate from being pushed into contact with the faceplate by atmospheric pressure when the space between the baseplate and the faceplate is evacuated. A plurality of emitters
106
are formed on the baseplate. The emitters
106
are constructed by thin film processes common to the semi-conductor industry. Millions of emitters
106
are formed on the baseplate
114
to provide a spatially uniform source of electrons.
In order to cause the emitters to emit electrons, a plurality of electrodes are also formed on the baseplate. The electrodes are typically formed in a grid fashion with the row electrodes
108
formed on the baseplate and the column electrodes
110
formed on an insulator
116
attached to the baseplate.
FIG. 2
is a 3-dimensional cross-section showing the construction of row electrodes
202
and column electrodes
204
. When a differential voltage is applied between a row electrode and a column electrode, an electric field is created at the tip of the emitters located at the intersection of the row and the column. The electric field at the tip of the emitter is controlled by the sum of the row and column voltages and is sufficiently high to cause electrons to tunnel through the surface of the emitter, into the vacuum, with no loss of energy. Virtually all the electrons bombard the phosphor, resulting in a bright display. Gray-scale or color can be achieved by varying the voltage applied to the column.
The number of row and column electrodes required will depend on the number of individual display elements, or “pixels,” to be addressed by the electrodes.
FIG. 3
illustrates the row and column electrodes required for a standard VGA display having 640 columns by 480 rows. Additionally, for a color display, each column requires a separate electrode for red, green, and blue elements. Therefore, a total of 1920 column electrodes are required.
A drive circuit is required to generate the desired voltage differential between each of the row and column electrodes. In a “passive matrix” drive scheme, each conductor requires a separate drive circuit. Referring still to
FIG. 3
, an image is created on an FED by sequentially “scanning” the rows. First, a voltage source
300
is used to apply a voltage row
302
-
1
to drive it to the appropriate voltage level. Second, all columns
304
-
1
to
304
-
1920
are driven to a voltage level related to the desired brightness of the relevant pixel using a circuit known as a “pulse height modulator” (not shown). The modulator sends pulses to its corresponding column electrode (
304
-
1
to
304
-
1920
) in which the height of the pulses depends on the desired brightness of the pixel. Third, all columns are turned off and row
302
-
1
is turned off. Finally, row
302
-
2
is then turned on and the process is repeated for rows
302
-
2
through
302
-
480
.
FIG. 3A
is a timing diagram showing the column pulse height in conjunction with example voltages at rows
1
and
2
.
However, this method of supplying a differential voltage to the electrodes is inefficient because each time a new row is scanned the columns must be discharged and then recharged to the desired voltages by the pulse height modulator. In fact, it is possible to calculate how much energy is required using this method.
For example, the above sequence occurs sixty times a second. So row
302
-
1
will also turn one and off sixty times in one second. A standard VGA display contains 640 columns by 480 rows. Therefore, the maximum pulse width of each row is 1/60(480)=34.7 microseconds.
Referring again to
FIG. 3
, a capacitance
306
will be associated with each intersection of a row and column. Therefore, in column
1
, the total capacitance is the parallel combination of C
1
R
1
+C
1
R
2
+C
1
R
3
+ . . . +C
1
R
480
, where CxRy is the capacitance at column x, row y. This total capacitance can equal as much as 1 nanofarad, possibly more, depending on the area of the display.
The amount of current required to drive each column is represented by the relationship:
&Dgr;V/&Dgr;T=I/C.
Example values for these parameters would be:
&Dgr;V=50 volts,
&Dgr;T=5 microseconds, and
C=1 nanofarad.
Therefore, solving the equation for I yields: I=10 milliamps. Accordingly, the power required to drive
1
column is calculated as follows:
P=IV·Duty Cycle=10 milliamps·50 volts·(5/34.7) microseconds=71 milliwatts.
Thus, the total power requirement for the FED would be:
P
total
=P·number of columns=71 milliwatts·1920=137 watts.
This type of power requirement represents a heavy drain on the batteries and renders them useless for such an application.
Attempting to overcome the above-mentioned problems by replacing the pulse width modulators with analog amplifier circuits has heretofore been impractical because continuously operating the amplifiers at the required current levels wastes large amounts of current in the devices which comprise the amplifier. Also, power amplifiers are packaged independently, whereas existing display drivers have multiple outputs per chip.
Therefore, it is an object of the present invention to overcome the above shortcomings.
SUMMARY OF THE INVENTION
In order to achieve the above objectives, an apparatus is provided for modulating a conductive element in an FED device from a first level to a second level. In one embodiment, the apparatus comprises a primary modulator having a first input connected to a first signal representative of the second level, an output connected to the conductive element, and a second input connected to a first signal representative of the output; and a connector of a modifying voltage to the output, the connector having a first input connected to a second signal representative of the second level and a second input connected to a second signal responsive to the output.
According to another embodiment of the invention, a field emission display is provided which has a plurality of row address lines which intersect with a plurality of column address lines, the intersections being associated with pixels, a group of emitters associated with the pixels, the emitters being responsive to a voltage difference between the r
Frenel Vanel
Hale and Dorr LLP
Micro)n Technology, Inc.
Shankar Vijay
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