Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
1998-12-21
2002-04-30
Munson, Gene M. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S752000
Reexamination Certificate
active
06380607
ABSTRACT:
This application claims the benefit of Korean Applications No.
97-80698
filed Dec. 31, 1997, and No.
98-30314
filed Jul. 28, 1998, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device and a method of fabricating the same. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for reducing a parasitic capacitance between data lines. Accordingly, a DRAM (Dynamic Random Access Memory) device having a stable performance and an improved data sensing capability is fabricated in the present invention.
2. Discussion of the Related Art
In a semiconductor device, aluminum is a choice of material for interconnection between gate electrodes, source/drain regions, and electrical contacts.
Generally, a wiring characteristic is deteriorated with a reduction in a device dimension or a power source. For example, in a gate electrode, a signal transmission is delayed due to a resistance increase. An operation speed is thus decreased. Also, a current intensity of an electrical contact is increased due to the resistance increase, thereby degrading a reliability of a wiring in the device. As a result, the increases in resistance and the current intensity cause an electromigration, which significantly degrades the reliability of the wiring in the device. Particularly in submicron devices, a RC (resistance-capacitance) transmission is delayed because a wiring resistance and a capacitance are increased due to micronization and reduction in a wiring pitch.
A metal wiring in a semiconductor device according to a background art will be explained with reference to the attached drawings.
FIG. 1
is a cross-sectional view illustrating the background art semiconductor device.
FIGS. 2A
to
2
E are cross-sectional views showing the process steps of fabricating method of the background art semiconductor device.
FIG. 3
is a circuit diagram of the background art semiconductor device.
In the DRAM, wordlines applying driving signals to cell transistors and bitlines applying data signals to cell capacitors are arranged to cross each other to have a higher integration. The background art semiconductor device will be explained with an emphasis on a conductive layer pattern (bitline).
Initially referring to
FIG. 1
, the background art semiconductor device is provided with a conductive layer pattern
12
on a semiconductor substrate
10
having cell transistors. The conductive layer pattern
12
is connected to source/drain of the cell transistors or another conductive layers. A second insulating layer
13
is formed on the semiconductor substrate
10
including the conductive layer pattern
12
, and a third insulating layer
14
for planarizing the device. At first insulating layer
11
, such as oxide, is provided between the conductive layer pattern
12
and the semiconductor substrate
10
for insulating the conductive pattern
12
from other regions.
A method of forming the aforementioned background art semiconductor device will be explained as follows.
Initially referring to
FIG. 2A
, an insulating layer
11
a
is formed on a semiconductor substrate
10
having cell transistors or another conductive layers formed thereon. A conductive layer
12
a
is formed on the insulating layer
11
a
for a metal line.
As shown in
FIG. 2B
, the conductive layer
12
a
and the insulating layer
11
a
are selectively etched to form a conductive layer pattern
12
and a first insulating layer pattern
11
, respectively.
In
FIG. 2C
, a second insulating layer
13
, such as oxide, is formed on the semiconductor substrate
10
including the conductive layer pattern
12
and the first insulating layer
11
.
A layer
14
a
having a good insulating characteristic and a fluidity, such as an SOG (spin on glass) layer, is formed over the semiconductor substrate in FIG.
2
D. In this process, the layer
14
a
is formed to completely fill the spaces between each conductive layer pattern
12
on the second insulating layer
13
.
Thereafter, the layer
14
a
is subjected to an anisotropic etching to expose an upper surface of the second insulating layer
13
, thereby completing a semiconductor device having a third insulating layer
14
, as shown in FIG.
2
E.
However, the semiconductor device fabricated by the aforementioned method has a parasitic capacitance Cb between the second and third insulating layers
13
and
14
. Generally, the second and third insulating layers
13
and
14
, such as oxide, have a dielectric constant of about 3.85.
A reading operation of the background art semiconductor device will be explained with reference to FIG.
3
.
A unit cell of a DRAM is provided with a cell transistor T
1
, a cell capacitor Cs having one electrode connected to a ground terminal and another electrode connected to one of electrodes of source/drain in the cell transistor T
1
. An S/A (sensing amplifier) for sensing and amplifying data in the cell through a bitline BL connected to one of the electrode of the source/drain in the cell transistor T
1
to output signals. As shown in
FIG. 3
, the aforementioned unit cell generates a parasitic capacitance Cb (bitline parasitic capacitance) during reading operation in the second and third insulating layers
13
and
14
between one side of the cell transistor T
1
and the S/A.
In reading data from the DRAM, when a voltage is applied to a wordline W/L through a gate of the cell transistor T
1
after a Vd/2 is precharged to the bitline B/L, the Vd/2 is also applied to the parasitic capacitance Cb. Upon applying the voltage to the wordline W/L to turn on the cell transistor T
1
, a charge in the cell capacitor Cs changes a voltage of the bitline B/L by Vs=(Vd/2)/(1+Cb/Cs). Thereafter, the sensing amplifier S/A compares voltages of the bitline B/L and a bitbarline {overscore (B)}/{overscore (L)} to output the compared value after amplifying the value. Vd, Cb, and Cs denote a voltage of a power source, a parasitic capacitance of the bitline, and a capacitance of the cell capacitor C
1
, respectively.
In order to have the Vs at least higher than 100 mV, both the Vd and the Cs should be increased, while the Cb should be decreased. However, there is a maximum value for Vd due to limitations in a transistor size and a low power consumption. Therefore, by reducing the Cb value, a data sensing capability can be much improved in the device. For instance, a dielectric constant of the second and third insulating layers
13
and
14
, such as oxide, between the conductive layer patterns
12
(bitlines) in the background art is about 3.85. The parasitic capacitance Cb may be represented as (&egr;S)/d, where &egr; is a dielectric constant of oxide, S is an area of the bitline, and d is a distance between the bitlines, respectively. Accordingly, the parasitic capacitance in the background art may be represented as Cb=(3.85×S)/d.
In a wiring in a semiconductor device according to the background art, a parasitic capacitance by the oxide layer between bitlines degrades a data sensing capability of the device. Since the parasitic capacitance is generated from a dielectric constant of oxide itself, it can be reduced by increasing both the source power voltage Vd and the capacitance of the cell capacitor Cs.
However, an increase in the source power voltage Vd is limited by size of the device and power consumption. Also, an increase in a cell capacitance is problematic because a fabricating process becomes complicated. Further, a reduction of the parasitic capacitance Cb is also practically impossible because of a dielectric constant of oxide.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a semiconductor device and a method of fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a wiring in a semiconductor device and a method of fabr
LG Semicon Co. Ltd.
Morgan & Lewis & Bockius, LLP
Munson Gene M.
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