Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
1997-10-29
2002-06-04
Vu, Viet D. (Department: 2154)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S227000, C710S071000
Reexamination Certificate
active
06401191
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to microcomputers.
BACKGROUND TO THE INVENTION
Single chip microcomputers are known including external communication ports so that the chip may be connected in a network including for example connection to a host microcomputer for use in debugging routines. Such systems are known in which each of the interconnected microcomputer chips has its own local memory. For speed of communication on on-chips it is common for bit packets to be transmitted between modules on a chip in a bit parallel format. However problems arise in both power consumption and available pin space in providing for external off-chip communications in the same parallel bit format as that used on-chip. Such microcomputers require access to instruction or code sequences and for efficient operation it is desirable for the instructions to be retrievable from locations within the address space of the CPU.
It is an object of the present invention to provide an improved microcomputer, and an improved method of operating a microcomputer system, in which external communications are simplified and instructions can be obtained from locations off-chip.
SUMMARY OF THE INVENTION
The invention provides a computer system comprising a microprocessor on a single integrated circuit chip connected to an external computer device, said integrated circuit chip having an on-chip CPU with a plurality of registers and a communication bus providing a parallel communication path between said CPU and a first memory local to the CPU, said integrated circuit further comprising an external communication port connected to said bus on the integrated circuit chip, said external computer device being connected to said external communication and having a second memory local to said external computer device, said port having an internal connection to the bus of an internal parallel signal format and an external connection of an external format less parallel than said internal format, said second memory being accessible by said CPU through said port, said port forming part of the memory address space of said CPU from which instructions may be fetched, whereby said port may be addressed by execution of an instruction by said CPU.
Preferably translation circuitry is arranged to translate bit packets between an on-chip bit parallel format and an external bit serial format.
Preferably said on-chip CPU includes circuitry for generating bit packets including a destination identifier within each packet, said external communication port having translation circuitry to translate bit packets between said internal and external formats while retaining identification of said destination.
Preferably said first and second memories each have addressable locations with addresses within the address space of said on-chip CPU and said translation circuitry is arranged to generate packets of said external format including an address within said second memory.
Said first memory may have software for execution by said on-chip CPU and said second memory may have software for execution by said on-chip CPU in a debugging routine for said on-chip CPU.
Said second memory may have software for execution by said external computer device in a debugging routine for said on-chip CPU.
Preferably said single integrated circuit chip has a plurality of CPUs on the same chip each connected to said communication bus whereby each CPU on said chip may address said external port.
Preferably said on-chip CPU includes pointer circuitry for identifying the location of a next instruction for execution by the CPU and said pointer circuitry is operable to point to an address in said second memory.
The invention includes a method of operating a computer system comprising a microprocessor on a single integrated circuit chip connected to an external computer device, said integrated circuit chip having an on-chip CPU with a plurality of registers and a communication bus providing a parallel communication path between said CPU and a first memory local to the CPU, said integrated circuit further comprising an external communication port connected to said bus on the integrated circuit chip, said external computer device being connected to said external communication and having a second memory local to said external computer device, which method comprises transmitting bit packets on said bus with an internal parallel signal format, translating said packets in said port to an external connection of an external format less parallel than said internal format, accessing said second memory by said CPU through said port, said port forming part of the memory address space of said CPU, and addressing said port by execution of an instruction by said CPU and thereby fetching an instruction from said second memory through said port.
Preferably bit packets are generated with a destination identifier within each packet, said external communication port translating bit packets between said internal and external formats while retaining identification of said destination.
Preferably said translation of bit packets is between an on-chip bit parallel format and an external bit serial format.
In one arrangement said first memory has software executed by said on-chip CPU and said second memory has software executed by said on-chip CPU in a debugging routine for said on-chip CPU.
Alternatively or additionally said second memory has software executed by said external computer device in a debugging routine for said on-chip CPU.
Preferably said on-chip CPU includes pointer circuitry for identifying the location of a next instruction for execution by the CPU and said pointer circuitry is loaded with a pointer value pointing to an address in said second memory.
REFERENCES:
patent: 5426769 (1995-06-01), Pawloski
patent: 5440698 (1995-08-01), Sindhu et al.
patent: 5525971 (1996-06-01), Flynn
patent: 5544311 (1996-08-01), Harenberg et al.
patent: 5574932 (1996-11-01), Sato et al.
patent: 5581779 (1996-12-01), Hall et al.
patent: 5687179 (1997-11-01), Whetsel, Jr. et al.
patent: 5724603 (1998-03-01), Nishiguchi
patent: 5978937 (1999-11-01), Miyamori et al.
patent: 0 720 092 (1996-07-01), None
Standard Search Report dated Sep. 23, 1997.
Byte, vol. 19, No. 6, Jun. 1, 1994, pp. 57-64,Multimedia Powerhouse, Karl M. Guttag.
Morris James H.
SGS-Thomson Microelectronics Limited
Skrivanek, Jr. Robert A.
Vu Viet D.
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