Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – And gettering of substrate
Reexamination Certificate
2000-12-20
2002-05-21
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
And gettering of substrate
C438S143000, C438S471000, C438S477000
Reexamination Certificate
active
06391738
ABSTRACT:
TECHNICAL FIELD
This invention relates to semiconductor processing methods, such as trench isolation methods.
BACKGROUND OF THE INVENTION
Integrated circuitry is typically fabricated on and within semiconductor substrates, such as bulk monocrystalline silicon wafers. To aid in interpretation of the claims that follow, the term “semiconductor substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductor substrates described above.
Electric components fabricated on substrates, and particularly bulk semiconductor wafers, are isolated from adjacent devices by insulating materials, such as silicon dioxide. One isolation technique uses shallow trench isolation, whereby trenches are cut into a substrate and are subsequently filled with an insulating material, such as, for example, silicon dioxide. In the context of this document, “shallow” shall refer to a distance of no greater than about 1 micron from an outermost surface of the substrate material within which an isolation region is received.
Prior art methods for forming trench isolation regions typically initially deposit a pad oxide layer and a silicon nitride layer over a semiconductive substrate. The substrate typically comprises a monocrystalline silicon wafer lightly doped with a p-type background dopant material. A photoresist layer is deposited onto the silicon nitride, and is processed to define desired trench shaped openings within the photoresist over the silicon nitride. Suitable etching steps are then conducted to etch trenches through the silicon nitride and pad oxide layer into the bulk monocrystalline silicon substrate, thus defining trenches which will be utilized for isolating various active regions on the substrate.
The photoresist is then stripped from the substrate, and the wafer is subjected to appropriate thermal oxidation conditions to oxide the substrate sidewalls within the trenches. One purpose of this oxidation is to round the bottom corners of the trenches to reduce stress at these corners during subsequent processing.
After sidewall oxidation, the trenches are typically filled with a dielectric material, such as by high density plasma chemical vapor deposition of an undoped oxide. Such deposition typically is conducted within a processing furnace having internal metal walls. Apparently, some of the metal from these chamber walls gets displaced, and ends up being deposited in the oxide on the substrate. The metals typically include one or more of aluminum, molybdenum, iron or chromium. Contamination concentration is typically on the order of 1×10
11
atoms/cm
3
. Presence of these metals in the finished product adversely affects device performance, such as creating refresh problems in DRAM circuitry and otherwise adversely impacting leakage characteristics of transistors formed within the active areas.
The high density plasma deposited oxide is typically not suitably dense as deposited. Accordingly in the prior art, it is subjected to a densification step at, for example, from about 800° C. to 1000° C. for 30 minutes in a chemically inert atmosphere. This causes the deposited oxide to densify and shrink to achieve desirable densification. Unfortunately, the deposited oxide and thermal oxide lining the trench sidewalls densify or shrink at different rates. This undesirably imparts stress into the deposited oxide layer and underlying substrate which also can have an adverse effect on the finished circuitry.
SUMMARY OF THE INVENTION
The invention includes semiconductor processing methods, including trench isolation. In one implementation, an oxide layer is deposited over a substrate. The deposited oxide layer is exposed to a chlorine-containing gas effective to getter metals outwardly therefrom. In one implementation, a dielectric layer, for example silicon dioxide, is plasma enhanced chemical vapor deposited over a substrate within a chamber comprising an internal metal surface under conditions effective to incorporate metal from the chamber surface within the dielectric layer. The dielectric layer is then exposed to a chlorine-containing gas effective to getter at least some of said metal outwardly therefrom. In one implementation, a trench isolation method comprises forming a series of isolation trenches into a semiconductive substrate. Silicon dioxide is chemical vapor deposited to within the trenches, with the silicon dioxide comprising metal impurity therein. The silicon dioxide within the trenches is densified using an atmosphere comprising chlorine which is effective to remove metal impurity from the silicon dioxide. In one implementation, some dielectric isolation material is chemical vapor deposited to within the trenches. After the chemical vapor deposition, the substrate is exposed to oxidation conditions effective to oxidize the trench sidewalls, with most preferably there having been no dedicated trench sidewall oxidation step conducted prior to the chemical vapor depositing.
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Dang Trung
Wells St. John P.S.
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