Fractional decimation filter using oversampled data

Details Fractional decimation filter using oversampled data Fractional decimation filter using oversampled data

2001-06-22

2002-08-13

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S143000, C375S316000

Reexamination Certificate

active

06433726

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of digital signal processing, and in particular to the down-sampling or decimation of data at a non-integer, or fractional, sample rate ratio.
2. Description of Related Art
Sample rate converters are common in the art. Data that is sampled at one rate is converted by a sample rate converter into data that is sampled at a second rate. Down-sampling, or decimation, is used to reduce the sampling rate, and up-sampling, or interpolation, is used to increase the sampling rate. Decreasing a sample rate by a factor of five, for example, can be effected by providing an output sample that corresponds to every fifth input sample. Increasing a sample rate by a factor of five is effected by repeating each input sample five times. Common down-sampling or up-sampling techniques use multiple input samples to generate each output sample. For example, in order to minimize noise and interference contribution to the output samples or to maximize the signal to noise ratio of the output samples of a down-sampler, a decimation filter determines the average, or weighted average, of multiple input samples as the output sample value. Additional input samples are often used in the up-sampling process in order to preserve the signal spectrum of the input sample. An interpolation filter provideses the value of each intermediate sample, based on an interpolation, or curve-fitting, of multiple input samples.
U.S. Pat. No. 5,548,540, “DECIMATION FILTER HAVING A SELECTABLE DECIMATION RATIO”, issued Aug. 20, 1996 to Daniel A. Staver and Donald T. McGrath, and incorporated by reference herein, discloses the selection of different sets of coefficients for averaging a plurality of input samples to determine each output sample. An integer ratio (n:1) between input and output samples is assumed, such that at each n
th
input sample, an output sample is produced.
International patent application, WO 99/56427, “SAMPLE RATE CONVERTER USING POLYNOMIAL INTERPOLATION”, filed Apr. 15, 1999 for Bruno J. G. Putzeys, and incorporated by reference herein, discloses the use of a polynomial approximation that is based on the phase of each output sample relative to the input samples, to determine output sample values corresponding to multiple input sample values. A phase-locked loop is used to provide a measure of the phase difference between the input and output samples. Different ratios of input to output sample rates are accommodated by the use of different sets of polynomial coefficients, and are not limited to integer ratios.
Given an input frequency of F
1
, and a desired output frequency of F
2
, the ratio F
1
/F
2
can be expressed or approximated as N+P/Q, where N, P, and Q are integers, N being the integer portion of the ratio, and P/Q being the fractional part. Fractional scaling via integer upscaling and downscaling can be achieved by first upscaling by a factor of Q(Q*F
1
), and then downscaling by a factor of N*Q+P to provide F
2
=Q*F
1
/(N*Q+P)=F
1
/(N+P/Q).
Commonly, oversampling is used to provide highly-accurate analog-to-digital (A/D) conversion, using a technique termed “delta-sigma” conversion. A delta-sigma converter digitizes an analog signal at a very high sampling rate, then filters the samples to remove the noise and interference that is introduced by the sampling process and the communication channel from a transmitter to a receiver, then downsamples the filtered data to the desired sample rate. In a conventional delta-sigma converter, the oversampling rate, Q, and downsample rate, N*Q+P, are selected so as to provide the desired output sampling rate. In some applications, however, the oversampling rate and the desired output sampling rate are independently specified, and a fractional downsampling is required. For example, the direct sampling of an intermediate frequency signal often requires that the sampling frequency has certain relation with the intermediate frequency.
U.S. Pat. No. 6,057,793, “DIGITAL DECIMATION FILTER AND METHOD FOR ACHIEVING FRACTIONAL DATA RATE REDUCTION WITH MINIMAL HARDWARE OR SOFTWARE OVERHEAD”, issued May 2, 2000 to Xue-Mei Gong, Tim J. Dupuis, Jinghui Lu, and Korhan Titizer, and incorporated by reference herein, discloses a combination of integer down-sampling and integer up-sampling to provide a fractional downsampling of oversampled data, by first down-sampling the data, then upscaling the data. Such multi-staged scaling, however, consumes power for each stage, is costly to fabricate, and may not be suitable for low-power and/or low-cost consumer applications, such as cellular telephones and other portable devices.
BRIEF SUMMARY OF THE INVENTION
It is an object of this invention to provide a decimator that provides fractional down-scaling. It is a further object of this invention to provide a decimator that provides fractional down-scaling in a single decimation stage. It is a further object of this invention to provide fractional down-scaling via an integer-decimation process. It is a further object of this invention to provide a decimator that is well suited for low-power and/or low-cost applications.
These objects and others are achieved by providing a decimator that selectively varies the output sampling rate such that the average output sampling rate corresponds to the desired output sampling rate. The output sampling rate varies such that an output sample is provided selectively after N input samples, or after N+1 input samples, to provide an output-to-input sampling ratio that is between N and N+1. This process introduces phase jitter as the sampling frequency varies between 1/N and 1/(N+1), but if the oversampling rate is high, and therefore N is high, as is typical of many applications that employ oversampling, the relative magnitude of the phase jitter is slight. A fractional accumulator is used to control whether the output occurs after N or N+1 input cycles, and is clocked by the input sampling clock, thereby minimizing the complexity of the embodiment.


REFERENCES:
patent: 5548540 (1996-08-01), Staver et al.
patent: 5619536 (1997-04-01), Gourgue
patent: 5621345 (1997-04-01), Lee et al.
patent: 5734683 (1998-03-01), Hulkko et al.
patent: 6057793 (2000-05-01), Gong et al.
patent: 6081216 (2000-06-01), May
patent: 6121910 (2000-09-01), Khoury et al.
patent: 6329939 (2001-12-01), Swaminathan et al.
patent: WO 99/56427 (1999-04-01), None
U.S. application No. 09/865,236, Fan, filed May 25, 2001, pending.

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