Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1998-07-16
2002-09-03
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S712000, C438S714000
Reexamination Certificate
active
06444584
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to composite multi-layer stack layers within microelectronics fabrications. More particularly, the present invention relates to plasma etch methods for forming patterned composite multi-layer stack layers within microelectronics fabrications.
2. Description of the Related Art
Microelectronics fabrications are formed from microelectronics substrates over which are formed patterned microelectronics conductor layers which are separated by microelectronics dielectric layers.
As microelectronics fabrication integration levels have increased and microelectronics fabrication device and patterned conductor layer dimensions have decreased, it has become increasingly important to efficiently form within microelectronics fabrications patterned composite polysilicon/silicon oxide/polysilicon stack layers. Such patterned composite polysilicon/silicon oxide/polysilicon stack layers are typically employed within microelectronics. fabrications for forming microelectronics structures such as but not limited to polysilicon capacitors, as well as gate electrodes employed within field effect transistors (FETs) such as electrically erasable programmable read only memory (EEPROM) field effect transistors (FETs) (which are also known as electrically alterable programmable read only memory (EAPROM) field effect transistors (FETs)).
While patterned composite polysilicon/silicon oxide/polysilicon stack layers are thus desirable within the art of microelectronics fabrication, patterned composite polysilicon/silicon oxide/polysilicon stack layers are nonetheless not formed entirely without problems within microelectronics fabrications. In particular, patterned composite polysilicon/silicon oxide/polysilicon stack layers when formed within microelectronics fabrications while employing a conventional plasma etch method employing a patterned photoresist etch mask layer often suffer from detrimental effects, such as microloading effects, when attempting to form the patterned composite polysilicon/silicon oxide/polysilicon stack layers with variable pattern density. Similarly, although microloading effects may often be attenuated when forming patterned composite polysilicon/silicon oxide/polysilicon stack layers while employing more sophisticated plasma etch methods employing multiple masking layers or plasma etchants, such alternative plasma etch methods typically provide enhanced process. complexity when forming patterned composite polysilicon/silicon oxide/polysilicon stack layers.
It is thus towards the goal of forming with enhanced process efficiency and attenuated microloading effect within a microelectronics fabrication a patterned composite polysilicon/silicon oxide/polysilicon stack layer that the present invention is more specifically directed. In a more general sense, the present invention is also directed towards the goal of forming with enhanced process efficiency and attenuated microloading effect within a microelectronics fabrication a patterned composite silicon/dielectric/silicon stack layer.
Various novel plasma etch methods have been disclosed within the art of microelectronics fabrication for forming patterned microelectronics layers within microelectronics fabrications.
For example, Becker et al., in U.S. Pat. No. 5,094,712, discloses a plasma etch method for efficiently forming an anisotropically patterned composite silicon oxide/tungsten silicide/polysilicon stack layer within an integrated circuit microelectronics fabrication. The method employs a single plasma reactor chamber within which there is sequentially and anisotropically etched: (1) a blanket silicon oxide layer while employing a carbon tetrafluoride, trifluoromethane and inert gas plasma to form a patterned silicon oxide layer; (2) a blanket tungsten silicide layer while employing a helium, oxygen and sulfur hexafluoride plasma to form a patterned tungsten silicide layer co-extensive with the patterned silicon oxide layer; and (3) a blanket polysilicon layer while employing a hydrogen bromide and chlorine plasma to form a patterned polysilicon layer co-extensive with the patterned tungsten silicide layer and the patterned silicon oxide layer.
In addition, Keller, in U.S. Pat. No. 5,346,586, discloses a plasma etch method for forming with high selectivity with respect to a silicon oxide gate dielectric layer within an integrated circuit microelectronics fabrication a patterned polycide gate electrode upon the silicon oxide gate dielectric layer within the integrated circuit microelectronics fabrication. The method employs an oxide hard mask layer from whose surface is first stripped while employing an ozone plasma stripping method a patterned photoresist layer employed in defining the oxide hard mask layer prior to employing the oxide hard mask layer as an etch mask layer for forming with selectivity with respect to the silicon oxide gate dielectric layer the polycide gate electrode upon the silicon oxide gate dielectric layer.
Finally, Maniar et al., in U.S. Pat. No. 5,525,542, discloses a method for forming within an integrated circuit microelectronics fabrication an accurately patterned reflective conductor layer while employing deep ultra-violet (DUV) photoexposure radiation of less than 300 nanometers when forming from a blanket photoresist layer a patterned photoresist layer employed in defining the accurately patterned reflective conductor layer. The method employs a blanket aluminum nitride layer formed interposed between the blanket reflective conductor layer and the blanket photoresist layer, where the blanket aluminum nitride layer serves as an anti-reflective coating (ARC) layer having particularly effective anti-reflective properties with respect to photo-exposure radiation within the deep ultra-violet (DUV) photoexposure radiation region of less than 300 nanometers.
Desirable in the art of microelectronics fabrication are methods through which there may efficiently and with attenuated microloading effect be formed patterned composite silicon/dielectric/silicon stack layers within microelectronics fabrications. More particularly desirable in the art of microelectronics fabrication are methods through which there may efficiently and with attenuated microloading effect be formed patterned composite polysilicon/silicon oxide/polysilicon stack layers within microelectronics fabrications.
It is towards the foregoing goals that the present invention is both generally and more specifically directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a method for forming within a microelectronics fabrication a patterned composite silicon/dielectric/silicon stack layer.
A second object of the present invention is to provide a method in accord with the first object of the present invention, where the patterned composite silicon/dielectric/silicon stack layer is efficiently formed with an attenuated microloading effect.
A third object of the present invention is to provide a method in accord with the first object of the present invention or the second object of the present invention, which method is readily commercially implemented.
In accord with the objects of the present invention, there is provided a method for forming within a microelectronics fabrication a patterned composite layer stack. To practice the method of the present invention, there is first provided a substrate. There is then formed over the substrate a blanket first silicon layer. There is then formed upon the blanket first silicon layer a blanket silicon containing dielectric layer. There is then formed upon the blanket silicon containing dielectric layer a blanket second silicon layer. There is then formed upon the blanket second silicon layer a blanket organic polymer anti-reflective coating (ARC) layer. There is then formed upon the blanket organic polymer anti-reflective coating (ARC) layer a patterned photoresist layer. Finally, there is then etched sequentially while employing the patterned photoresist layer as a photoresist etc
Ackerman Stephen B.
Saile George O.
Taiwan Semiconductor Manufacturing Company
Utech Benjamin L.
Vinh Lan
LandOfFree
Plasma etch method for forming composite... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Plasma etch method for forming composite..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Plasma etch method for forming composite... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2909194