Metal treatment – Process of modifying or maintaining internal physical... – Chemical-heat removing or burning of metal
Patent
1973-03-12
1976-03-16
Rutledge, L. Dewayne
Metal treatment
Process of modifying or maintaining internal physical...
Chemical-heat removing or burning of metal
29577, 29578, 29580, 148187, 156 7, 156 17, 156605, 2041296, 20412965, 357 42, 357 44, 357 49, 357 51, 427 93, 01L 2712, H01L 2120, H01L 2176, H01L 2702
Patent
active
039444473
ABSTRACT:
Structure: An integrated circuit structure with full dielectric isolation comprising a supporting substrate having a planar surface of dielectric material and a semiconductor layer on said dielectric surface which forms a planar interface with the surface. Regions of oxidized silicon extend through the layer from said interface, surrounding and dielectrically isolating pockets of silicon in the layer; the oxidized silicon regions extend to the upper surface of the semiconductor layer where they are substantially co-planar with the silicon pockets. The devices of the integrated circuit are formed in said silicon pockets.
Method: The structure is fabricated by a novel method wherein a lightly doped silicon layer is deposited on a highly doped silicon substrate; surrounding oxidized silicon regions are then formed by selectively thermally oxidizing portions of the silicon layer to form oxide regions which are co-extensive with the oxidized areas and, thus, are co-planar with the remaining silicon pockets at both surfaces of the layer; a member having a dielectric surface interfacing with the silicon layer is formed, and the silicon substrate is removed by preferential electrochemical anodic etching to leave the silicon layer having the oxidized regions surrounding spaced silicon pockets mounted on said member.
REFERENCES:
patent: 3423255 (1969-01-01), Joyce
patent: 3534234 (1970-10-01), Clevenger
patent: 3602981 (1971-09-01), Kooi
patent: 3602982 (1971-09-01), Kooi
patent: 3640806 (1972-02-01), Watanabe et al.
stern et al., "Fabrication of Planar Arrays--Insulating Barriers" I.B.M. Tech. Discl. Bull., Vol. 7, No. 11, Apr. 1965, p. 1103.
Chang et al., "Fabricating NPN and PNP--single Device" Ibid., Vol. 12, No. 11, Apr. 1970, pp. 1994-1995.
Appels et al., "Local Oxidation of Silicon--Technology" Philips Res. Repts., Vol. 25, 1970, pp. 118-132.
Magdo Ingrid E.
Magdo Steven
IBM Corporation
Kraft J. B.
Rutledge L. Dewayne
Saba W. G.
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