Coded data generation or conversion – Digital code to digital code converters
Reexamination Certificate
2001-01-30
2002-05-21
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
C341S106000, C341S058000
Reexamination Certificate
active
06392566
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a code modulator and a code modulation method, particularly to a modulator and a modulation method for modulating input codes on the basis of a table in which modulation codes corresponding to input codes are stored, and more particularly to a modulator and a modulation method for modulating codes to be written in optical disks such as DVDs (Digital Video Disks).
2. Description of Related Art
In order to modulate code in a DVD, a modulation system referred to as an 8/16 modulation is used. The 8/16 modulation converts an 8-bit input code into a 16-bit code, and records the converted 16-bit code in succession to a 16-bit code obtained by converting the immediately previous input code. The code forms a bit string of bits having a “0” value and bits having a “1” value. In the bit string, the minimum number of bits having a “0” value positioned between two bits having a “1” value is defined as 2 and the maximum is defined as 10, which is hereinafter referred to as RLL (2.10) requirements. Note that RLL is an abbreviation for Run Length Limited. The conversion of an 8-bit code to a 16-bit code is carried out on the basis of a conversion table in which conversion codes corresponding to input codes are stored.
FIG. 10
shows a structural example of a code modulator
80
for executing the 8/16 modulation. This modulator
80
converts an 8-bit (0 to 255) input code to a 16-bit code, and includes a conversion table
84
and a code conversion section
82
.
The conversion table
84
includes a main table and a sub-table. As shown in
FIG. 11
, the main table stores a plurality of conversion codes (STATE
1
,
2
,
3
,
4
) corresponding to respective input codes of 0 to 255. As shown in Table
12
, the sub-table stores a plurality of conversion codes (STATE
1
,
2
,
3
,
4
) corresponding to respective input codes of 0 to 87. Normally, a ROM (Read Only Memory) is used as the conversion table
4
.
A value NS (NS=1, 2, 3 or 4) is added to each conversion code. When a conversion code is used in a conversion of an input code, the value NS indicates a STATE of a conversion code that is used for the conversion of the next input code. For example, in the case where a conversion code having an input of 255 and a STATE of “3” is used, the NS value of that conversion code is “2”. Therefore, in the next input (for example, 89) code conversion, the conversion code having an input of 89 and a STATE of “2” is used.
Next, an explanation of the next STATE (NS) and respective conversion codes will be given. In this embodiment, where the last bit or the last two bits of the conversion code used in an input code conversion is/are “1” or “1 0”, a conversion code of STATE
1
is designated as the conversion code used for the next code conversion. In this case, in order to satisfy the RLL (2.10) requirements, the first two bits to nine bits of bit string of the conversion code of STATE
1
are continuous “0”s.
Where last two bits to five bits of the conversion code used in an input code conversion are continuous “0”s, a conversion code of STATE
2
or STATE
3
is designated as the conversion code used for the next code conversion in this embodiment. In order to satisfy the RLL (2.10) requirements, the first bit of the conversion codes of STATE
2
and STATE
3
are “1” or the first five bits of the conversion codes of STATE
2
and STATE
3
are continuous “0”s. In this case, the first bit and the 13th bit of the conversion code of STATE
2
are always “0”, and the first bit and/or the 13th bit of the conversion code of STATE
3
is/are always “1”.
Where the last six bits to nine bits of the conversion code used in an input code conversion are continuous “0”s, a conversion code of STATE
4
is designated as the conversion code used for the next code conversion in this embodiment. In this case, in order to satisfy the RLL (2. 10) requirements, the first one bit or the first two bits of the conversion code of STATE
4
is “1” or “0 1”.
In this manner, a conversion code of STATE designated by the NS (the next STATE) added to each conversion code is used for the conversion of the next input code, so that the RLL (2.10) requirements can be always satisfied.
The code conversion section
82
comprises: an arithmetic unit
22
for calculating DSV (digital sum value), which will be described later; a comparator
24
for comparing DSV values; a memory (storage device)
28
for storing DSV value obtained up to the current conversion (to be described later) and STATE (NS) of the conversion code to be used for the next code conversion as described above; and a control section
26
for specifying STATE to be used in a next code conversion on the basis of the NS value of the memory
28
and converting the input code by controlling the arithmetic unit
22
and the comparator
24
.
Wherever an input code is converted, the NS value (1, 2, 3 or 4) added to the conversion code is stored in the memory
28
. According to the NS value stored in the memory
28
, it is possible to specify which conversion code to be used among STATE
1
to STATE
4
for the next input code conversion.
In this manner, according to the NS value stored in the memory
28
, it is possible to specify a conversion code to be used among a plurality of conversion codes (STATES
1
to
4
) corresponding to an input code. However, as shown in
FIGS. 11 and 12
, there are two kinds of conversion codes corresponding to input codes of 0 to 87; one in a main table and the other in a sub-table. For this reason, either one of them needs to be selected. The conversion procedures in the case of input codes of 0 to 87 are different from those in the case of input codes of 88 to 255.
Where an input code is any one of 0 to 87, the corresponding conversion code is selected from either the main table or the sub-table. The selection of the conversion code is carried out by using the DSV values. As shown in
FIG. 13
, the DSV value is the integral of bit outputs whose polarity is inverted wherever “1” appears in the code. In the actual selection, the accumulated value of DSV values of conversion codes that have been used up to the current code conversion (hereinafter also referred to as DSV value obtained up to the current conversion). The DSV value up to the current conversion is calculated in the arithmetic unit
22
wherever an input code is converted, and then stored in the memory
28
. The selection of the conversion code is carried out so that the DSV value up to the current conversion may approach zero.
Specifically, a conversion code can be specified by reading an NS value (a next STATE) from the memory
28
on the basis of the input code and STATE. A conversion code specified in the main table is read, and then a DSV value in the case of using this conversion code is obtained. This DSV value is obtained by adding the DSV of the conversion code itself to the DSV value obtained up to the current conversion. In the same manner, a conversion code specified in the sub-table is read, and then a DSV value corresponding to this conversion code is obtained. Thereafter, the two DSV values are compared, and the conversion code closer to zero is selected.
If the absolute values of the two DSV values are equal and the one closer to zero is not specified, the one having more number of polarity inversions is selected. If the numbers of polarity inversions are equal to each other, the one in the main table is selected. Thus, when the absolute values of the two DSV values are equal, a conversion code can be always selected from the main table without consideration of the number of polarity inversions, so that the process can be simplified.
Where an input code is in a range of 88 to 225, the corresponding conversion code is selected from the main table. In this case, however, when STATE
1
is specified on the basis of the NS value of the memory
28
, the conversion code of STATE
4
may be used instead of that of STATE
1
. In the same manner, when STATE
4
is specified, the conversion c
Feece Ron
Jean-Pierre Peguy
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