Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2001-02-05
2002-06-11
Nelms, David (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
C365S201000
Reexamination Certificate
active
06404663
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit comprising a memory cell for reading and writing data, more particularly, to a technology for optimizing a timing of a controlling signal which controls an internal circuit.
The present invention relates to a semiconductor integrated circuit having a testing mode, more particularly, to a technology for modifying an operation timing of an internal circuit in a testing mode.
2. Description of the Related Art
Integration levels and operation speeds of semiconductor integrated circuits such as microcomputers and DRAM's have been improving. Recently, timing margins of controlling signals used in internal circuits have been reduced due to the increasing operation speeds, and timing design considering wiring length or the like within a chip has been carried out.
FIG. 1
shows a chip layout of an SDRAM (Synchronous DRAM) among semiconductor integrated circuits of this kind, which operates in synchronization with a clock signal.
FIG. 1
shows circuits related to data input/output in accordance with a column address.
An SDRAM
1
comprises four pairs of memory core units
2
laid out in mirror symmetry in each of the pairs. A peripheral circuit
3
(the stippled portion in
FIG. 1
) is arranged at the center of the SDRAM
1
in a cross-like shape along the vertical and horizontal directions of the SDRAM
1
.
Each of the memory core units
2
comprises a plurality of main-decoders
4
, sense amplifiers
5
, switching circuits
6
, memory cells
7
, sense buffers
8
, and write amplifiers
9
. (Hereinafter, explanation of the plurality of the circuits above and a pad described below will be given for each single unit of the circuits, such as “the sense amplifier 5” instead of “each of the sense amplifiers 5”, except for some cases of the sense buffers
8
and the write amplifiers
9
where each buffer or amplifier is specified by a reference code.) A pre-decoder
10
is arranged between each pair of the memory core units
2
laid out in mirror symmetry.
Pads
11
for receiving and transmitting signals from and to the exterior of the chip are arranged within the peripheral circuit
3
along the horizontal direction of FIG.
1
. Wirings of a read data signal RDBZ, a write data signal WDBZ, testing read data signals TRDBZ and TRDBX, and a testing write data signal TWDBZ is arranged within the peripheral circuit
3
along the horizontal direction of FIG.
1
. The peripheral circuit
3
comprises a data input/output circuit
12
, a clock buffer
13
, a clock pulse generator
14
, a timing controlling circuit
15
, a resetting circuit
16
, a testing circuit
17
, a controlling circuit
18
, or the like.
The clock buffer
13
receives a clock signal CLK from the exterior through the pad
11
, and outputs an internal clock signal CLKZ. The clock pulse generator
14
receives the internal clock signal CLKZ and outputs a clock pulse signal CEPZ. The timing controlling circuit
15
receives the clock pulse signal CEPZ and outputs a read controlling signal SEBZ and a write controlling signal WAEZ. The resetting circuit
16
receives the read controlling signal SEBZ, the read data signal RDBZ, and the testing read data signals TRDBZ and TRDBX. The data input/output circuit
12
receives the read data signal RDBZ, the write data signal WDBZ, the testing read data signals TRDBZ and TRDBX and the testing write data signal TWDBZ. The data input/output circuit
12
also receives a data signal DQ through the pad
11
. The testing circuit
17
outputs a testing signal TESZ. The testing signal TESZ is supplied to the data input/output circuit
12
, the resetting circuit
16
, the sense amplifier
8
, and the write amplifier
9
, which is not shown in FIG.
1
.
The pre-decoder
10
receives the clock pulse signal CEPZ and a row address signal which is not shown in FIG.
1
. The pre-decoder
10
outputs a column decoding signal CAZ to the main-decoder
4
. A portion of wiring of the clock pulse signal CEPZ is formed horizontally along the memory core unit
2
, and wiring length thereof is long. Therefore, a load of the wiring of the clock pulse signal CEPZ is large. Likewise, wiring of the column decoding signal CAZ is formed vertically within the main-decoder
4
, and has long length. Therefore, a load of the wiring of the column decoding signal is also large.
The main-decoder
4
receives the column decoding signal CAZ and outputs a column selecting signal CLZ. The sense amplifier
5
receives bit line signals BLX and BLZ. The bit line signals BLX and BLZ are complementary signals.
The memory cell
7
receives the bit line signals BLX and BLZ. The switching circuit
6
receives the column selecting signal CLZ, the bit line signals BLX and BLZ and internal data signals GDBZ and GDBX. The sense buffer
8
receives the internal data signals GDBZ and GDBX and outputs the read data signal RDBZ and the testing read data signals TRDBZ and TRDBX. The write amplifier
9
receives the write data signal WDBZ and the testing write data signal TWDB, and outputs the internal data signals GDBZ and GDBX.
A J-shaped arrow A
1
shown in the memory core unit
2
in
FIG. 1
means that data read from the memory cell
7
are amplified by the sense amplifier
5
as the bit line signals BLZ and BLX and supplied to the sense buffer
8
through the switching circuit
6
. A J-shaped arrow A
2
means that write data output from the write amplifier
9
through the switching circuit
6
is supplied to the sense amplifier
5
as the bit line signals BLZ and BLX and written to the memory cell
7
.
Each signal line described above is also connected to the pre-decoders
10
and to the memory core units
2
where the signal lines are not shown in FIG.
1
.
Each signal line or wiring shown by a thick line in
FIG. 1
comprises a plurality of lines. For example, the read data signal RDBZ comprises read data signals RDB
0
Z, RDB
1
Z, RDB
2
Z, and RDB
3
Z, and the write data signal WDBZ comprises write data signals WDB
0
Z, WDB
1
Z, WDB
2
Z, and WDB
3
Z.
The signals suffixed with “Z” mean signals of positive logic, while the signals suffixed with “X” are signals of negative logic.
FIG. 2
shows main circuits and flow of main signals which are related to a column address.
The switching circuit
6
comprises an nMOS transistor. The gate of the nMOS transistor receives the column selecting signal CLZ and the source and the drain thereof receive the bit line signals BLZ and BLX and the internal data signals GDBZ and GDBX, respectively. Hereinafter, an nMOS transistor and a pMOS transistor are respectively called an nMOS and a pMOS for short.
FIG. 3
shows the clock buffer
13
in detail.
The clock buffer
13
comprises a differential amplifier
19
for comparing the clock signal CLK input from the exterior with a reference voltage VREF, and a pulse generator
20
comprising an inverter and a NAND gate. The reference voltage VREF is set to a half of a supply voltage VCC (2.5V).
The differential amplifier
19
has voltage outputting parts
21
and
22
symmetric to each other and each having a pMOS and an nMOS connected in series. The gates of nMOS'es
21
a
and
22
a
of the voltage outputting parts
21
and
22
receive the clock signal CLK and the reference voltage VREF, respectively. The sources of the nMOS'es
21
a
and
22
a
are connected to a ground line VSS through an nMOS
23
. The gate of the nMOS
23
is connected to a power supply line VCC. A node ND
1
connecting the nMOS
21
a
to the pMOS
21
b
of the voltage outputting part
21
is connected to the input of the pulse generator
20
.
The sources of the pMOS'es
21
b
and
22
b
are connected to the power supply line VCC. The gates of the pMOS'es
21
b
and
22
b
are connected to the drain (a node ND
2
) of the pMOS
22
b.
The voltage outputting parts
21
and
22
form a current mirror circuit.
The pulse generator
20
comprises an inverter
20
a
and inverter rows
20
b
and
20
c
each connecting three inverters in cascade, and a 2-in
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Nelms David
Tran M.
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