Metal fusion bonding – Process – With protecting of work or filler or applying flux
Reexamination Certificate
2001-04-25
2002-07-09
Dunn, Tom (Department: 1725)
Metal fusion bonding
Process
With protecting of work or filler or applying flux
C228S180220, C228S254000, C257S737000, C438S613000
Reexamination Certificate
active
06415974
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89115393, filed Aug. 01, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor device fabrication, and more particularly, to a structure of solder bumps with improved coplanarity and a method of forming solder bumps with improved coplanarity.
2. Description of the Related Art
With recent advances in semiconductor fabrication technology and the increasing demand for improving connection density of semiconductor applications, various techniques have been developed for having a large number of input/out points (I/Os) in a device. The flip-chip technology is being utilized to allow more I/Os on an integrated circuit device.
In the packaging industry, the flip-chip packaging can reduce inductance while providing a higher interconnection density and ultimately, a lower cost. The flip-chip technique utilizes solder bumps instead of wires to connect bonding pads on an integrated circuit (IC) device to bonding pads on an IC package or to mounting pads on a circuit board. Since the flip chip technique is faster, denser, thinner, lighter and has a low cost package, one can expect the flip-chip technique to replace wire-bonding. In order to connect the solder bumps to an IC package or directly to a circuit board, it is important that the solder bumps are formed with a uniform height across a semiconductor wafer so that in the later step of bonding a IC device to the IC package can be performed efficiently. However, it is hard to electroplate solder bumps of uniform height all the way across a wafer. One problem with electroplating that contributes to solder bumps being formed at a non-uniform height is the uneven distribution of plating current density across a wafer. The uneven distribution of plating current density causes a thicker layer of solder to be plated over areas where the current density is higher and a thinner layer of solder to be plated over areas where the current density is lower. When the solder bumps having various heights across a wafer, there will be difficulty in the bonding process and the efficiency, reliability and yield of the production will be affected due to the reworked or scraped chips.
The limitations of and a further explanation of the conventional plating technology is disclosed below in reference to FIG.
1
A and
FIG. 1B
FIG.
1
A and
FIG. 1B
are schematic cross-sectional views of a conventional structure of bumps.
FIG. 1A
illustrates bonding pads formed on a substrate to be used as connecting points for an external circuit. A passivation layer
108
(or an insulating layer) is formed on the bonding pads
102
, wherein only a portion of each bonding pad
102
is exposed.
An under ball metallurgy (UBM) layer
104
is formed on the bonding pad
102
, wherein the UBM layer has an area
132
or
134
. The UBM layer comprises a barrier layer
103
and a plating layer
105
, whereby the barrier layer
104
is used to prevent some ions of the bumps from penetrating the bonding pad
102
. If the bonding pad is damaged, the device will be affected. The plating layer
105
is to improve the adhesion between the bumps and the bonding pad
102
.
Solders
122
a
and
122
b
are formed on the UBM layer
104
by a conventional process, wherein the solders are formed unevenly due to the non-uniform plating distribution on the surface of the UBM layer.
FIG. 1B
illustrates different heights of solder bumps
106
a
,
106
b
formed during a reflow process, wherein the height of solder bump
106
b
is higher than the bump
106
a
because the volume of solder
122
b
is more than the volume of solder
122
a.
Different heights of the solder bumps cause bad bonding between chips to a package carriers, and bad connections will also affect the device functions even damaging the devices.
SUMMARY OF INVENTION
It is an object of the present invention to provide an improved UBM structure of forming uniform solder bumps on integrated circuit devices. Wherein the improved UBM structure comprises: a substrate having at least an active surface, which comprises a plurality of bonding pads and those bonding pads serve as connecting nodes to external circuits. A passivation layer is formed over the active surface of the substrate, wherein portions of the bonding pads are exposed by the passivation layer. A plurality of Under Ball Metallurgy (UBM) layers formed on the exposed portions of the bonding pads, wherein each of the UBM layer having a different area and being electrically connected to the bonding pads. A plurality of solder bumps formed on the UBM layers, wherein the solder bumps having various sizes are formed substantially with the same height.
It is another object of the present invention to provide an improved method of forming uniform solder bumps on integrated circuit devices. The improved method of forming uniform solder bumps comprises a substrate having at least an active surface is provided and a plurality of bonding pads are formed on the active surface of the substrate. A passviation layer is formed over the active surface of the substrate, wherein portions of the bonding pads are exposed by the passviation layer. A plurality of Under Ball Metallurgy (UBM) layers is formed on the exposed portions of the bonding pads. A mask layer having a plurality of openings is formed on the exposed bonding pads, wherein the openings have various sizes. A plurality of solder bumps are formed on the UBM layers, wherein the solder bumps are substantially equivalent in volume and height.
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Dunn Tom
Huang Jiawei
Siliconware Precision Industries Co. Ltd.
Stoner Kiley
LandOfFree
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