Delay lock loop and update method with limited drift and...

Details Delay lock loop and update method with limited drift and... Delay lock loop and update method with limited drift and...

2001-01-11

2002-09-24

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S158000

Reexamination Certificate

active

06456130

ABSTRACT:

BACKGROUND
1. Technical Field
This disclosure relates to delay lock loops, and more particularly, to an apparatus and method for limiting drift due to temperature and noise variation while reducing power consumption of the apparatus.
2. Description of the Related Art
Semiconductor memories, such as synchronous dynamic random access memories (SDRAMs) and specific Double Data Rate (DDR) memories, typically include delay lock loops (DLLs). DLLs function to cancel on-chip amplification and buffering delays, and DLLs improve input/output timing margins. DDR SDRAMs are designed such that READ/WRITE data on output lines (DQ pins) are synchronized to a system clock (e.g., CK/bCK).
Referring to
FIG. 1
, a schematic diagram of a conventional DLL circuit
8
includes a receiver
10
for receiving clock input signals, CK and bCK. An input driver
12
receives an amplified clock pulse from receiver
10
and conditions the signal as is known in the art (e.g., pulse generation). Input driver
12
outputs the clock signal to a delay line
14
which includes a plurality of delay elements and a phase detector (PD)
16
(Ref_clock). Elements of delay line
14
include inverter chains or other delay elements to delay the clock signal in accordance with a phase comparison between Ref_clock and a feedback clock signal (FB_clock, which is delayed in accordance with elements
14
). Phase detector
16
receives both Ref_clock and FB_clock signals and compares the phase to determine delay differences between the signals. Phase detector
16
generates a control signal, which indicates to a delay line (DL) control unit
20
to increment (+), decrement (−) or lock (0) delay elements in delay line
14
. DL control unit
20
(also called a pointer control unit) responds by sending a signal to increment/decrement (inc/dec) delay line
14
or by locking the DLL
8
. The output clock signal of delay line
14
is employed to drive an output pin driver (QS or DQ) driver
22
. Driver
22
is employed to clock data transfer from/to the chip.
For power reduction, a Power Down Mode is employed in which the Clock/DLL path is disabled and pointer control unit
20
maintains its settings. DLL temperature and noise drifts are experienced between entry and exit of the power down mode.
In DDR SDRAMs, DLLs are required to synchronize the output pins (e.g., DQs) to the system clock CK/bCK in a read operation. DDR SDRAM specifications may optionally require DLL updates with every Auto Refresh (AR) cycle. Auto refresh (AR) cycles refresh memory cells according to word lines. AR cycles may include burst cycles where memory cells associated with all gate lines are refreshed in a same time window. AR cycles may also be performed on word lines a little at a time (several word lines at a time, i.e., in pieces) over a longer time window. The DLL off function reduces the DLL current in the Power Down mode. The problem with updating only during AR cycles is the DLL drift due to temperature and noise variations in between these AR cycles. This drift gets worse during Power Down mode while the DLL is disabled. Measurements on the chip show DLL drift between AR cycles for 8 burst AR cycles.
DLL updates enabled during Auto Refresh cycles and DLL drift due to temperature and noise between AR cycles is possible, causing variations in the data valid window during read cycles. Therefore, a need exists for an apparatus and method for reducing drift in delay lock loop circuits.
SUMMARY OF THE INVENTION
A delay lock loop circuit, in accordance with the present invention includes a delay lock loop unit having a power down mode. The delay lock loop unit includes a delay line having an input and an output. The input receives a first clock signal to generate a modified clock signal at the output. A phase detector is coupled to the input and the output of the delay line for comparing the first clock signal and the modified clock signal. A delay line control unit is coupled to the phase detector and the delay line for adjusting delay in the delay line in accordance with a control signal from the phase detector. A counter circuit is included for updating the delay lock loop unit to account for delay line drift during the power down mode by periodically generating an update signal which enables the delay lock loop unit for updating.
A delay lock loop circuit for driving data for a memory chip includes a receiver for outputting an amplified clock signal to an input driver circuit. The input driver is coupled to the receiver and generates clock pulses for a first clock signal. A delay lock loop unit has a power down mode and a normal operation mode. A delay line has an input and an output. The input of the delay line receives the first clock signal to generate a modified clock signal at the output. A phase detector is coupled to the input and the output of the delay line for comparing the first clock signal and the modified clock signal and generates a control signal in accordance with the comparison. A delay line control unit is coupled to the phase detector and the delay line to adjust delay in the delay line in accordance with the control signal from the phase detector. A clock counter circuit is included for updating the delay lock loop unit to account for delay line drift during the power down mode by periodically generating an update signal, which permits the delay lock loop unit to update in the power down mode. A data driver is enabled in the normal operation mode by the modified clock to drive data for the memory chip in accordance with the modified clock signal.
In other embodiments, the counter circuit may include an oscillator for tracking time between update signals. The oscillator may include an operating frequency of less than or equal to 1 MHz. The counter circuit may include a counter coupled to the oscillator for counting a number of clock cycles such that when the number of clock cycles exceeds a threshold the update signal is generated. A memory device may be coupled to the counter for providing the threshold such that the threshold defines the time elapsed between update signals. The memory device may include at least one of a fuse block and a metal option. The counter circuit is preferably turned on when the delay lock unit is locked. The predetermined number of cycles enables the unlock signal between auto refresh (AR) cycles.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.


REFERENCES:
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patent: 6043694 (2000-03-01), Dortu
patent: 6047346 (2000-04-01), Lau et al.
patent: 6100733 (2000-08-01), Dortu et al.
patent: 6125157 (2000-09-01), Donnelly et al.
patent: 6127866 (2000-10-01), Chu et al.
patent: 6137327 (2000-10-01), Schnell
patent: 6140854 (2000-10-01), Coddington et al.
patent: 6198689 (2001-03-01), Yamazaki et al.

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